Jasper Design Automation’s Rajeev Ranjan Presents Paper On Behavioral Indexing at DesignCon 2009

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—January 28, 2009— Jasper Design Automation, provider of the most advanced formal technology solutions, today announced that its chief technology officer, Rajeev Ranjan, will present a paper at DesignCon 2009 discussing a promising new technology, Behavioral Indexing, for enabling efficient IP design reuse.


Rajeev Ranjan is the Chief Technology Officer of Jasper Design Automation and is responsible for developing Jasper’s overall technology vision and driving the business value of formal technology. Prior to joining Jasper, Rajeev was CTO and VP of Engineering at Real Intent, where he led the development of their products and set the company’s technical direction. Before joining Real Intent, he was in the Advanced Technology Group at Synopsys, where he co-developed the prototype for Magellan, Synopsys’s formal-assisted simulation product. Rajeev has been active in the area of formal verification for more than 17 years, and has published numerous articles and holds a number of patents in the area of functional verification.


This session is part of DesignCon’s new IP Summit. The paper is entitled, “Toward Harnessing the True Potential of IP Reuse” and will feature a discussion on how Behavioral Indexing can be used to address the root problems of comprehension, modification, and re-verification of IP for efficient reuse.
“Behavioral Indexing will enable breakthroughs in design comprehension, reuse, and IP delivery, solving many business problems associated with IP, whether commercial or internally-developed,” stated Rajeev. “By leveraging this technology even earlier in the design flow, designs will be built to enable easy future design reuse and modification, truly harnessing the complete potential that design reuse has to offer for speeding highly innovative products to market.”


Tuesday, February 3rd, 11:05 am – 11:45 am


DesignCon 2009, Santa Clara Convention Center, Santa Clara California, Track 3: IP Re-Use and Integration.

For details visit: http://www.designcon.com/2009/attendees/schedule/3_ta_4.asp .

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