What: Tensilica, Inc. will present a live webcast, “How to Avoid the Traps and Pitfalls of SOC Design,” that includes a frank discussion of the ways to avoid SOC design traps and pitfalls and lead a team to success. This Webinar will help participants make better SOC design choices. No product pitches. No selling. No boring descriptions of “my wonderful new product.” Just information to help a design team find its way through the convoluted maze of today’s SOC design challenges.
Who: The presenters for the November 19th broadcast will be Steve Leibson, technology evangelist, Tensilica, and Grant Martin, chief scientist, Tensilica.
When: The live webcast will take place on Wednesday, November 19th at 11:00 a.m. PT / 2:00 p.m. ET. Afterwards, it will be available on demand from the EDN archives.
Where: To attend the webcast, participants can register by going to http://www.tensilica.com/news_events/events.htm
Tensilica, Inc., is the recognized leader in customizable dataplane processors. Dataplane Processor Units (DPUs) consist of performance intensive DSP (audio, video, imaging, and baseband signal processing) and embedded RISC processing functions (security, networking, and deeply embedded control). The automated design tools behind all of Tensilica’s application specific processor cores enable rapid customization to meet specific data-plane performance targets. Tensilica’s DSPs and processors power top tier semiconductor companies, innovative start-ups, and system OEMs for high-volume products including mobile phones, consumer electronics devices (including portable media players, digital TV, and broadband set top boxes), computers, and storage, networking and communications equipment. For more information on Tensilica’s patented benchmark-proven DPUs visit www.tensilica.com.
for Tensilica, Inc.
Erika Powelson, 831-424-1811