The Best of Times, The Worst of Time: Part 2

Do not tell me this industry is dead in the water, or withering in the face of a global downturn. People are working hard, hoping to stay employed, and bringing energy, intelligent and indefatigable optimism to their work. I’m aware that many have been laid off, but all of us have been through that. We have to believe there is a future here, given the depth and breadth of the following news out of a variety of companies:

* CEDA and ACM SIGDA together announced a call for nominations for the A. Richard Newton Technical Impact Award in Electronic Design Automation. Per the Press Release: “The yearly award for outstanding technical contributions honors the late Dr. Richard Newton, a luminary in design automation academia and industry, and dean of engineering at U.C. Berkeley, who died in 2007. The award will be presented to an individual or individuals for outstanding technical contributions to EDA, recognized over a significant period of time. Qualifications will be based on a high-impact, seminal paper published by either ACM or IEEE nominees at least 10 years ago. Nominations are being accepted until May 15, 2009.”

* Accellera announced voting has confirmed solid, ongoing leadership for this pivotal language standards body: Sun’s Shrenik Mehta as Chair; Mentor Graphics’ Dennis Brophy as Vice-Chair; Synopsys’ Karen Bartleson as Secretary; and Magma’s Yatin Trivedi as treasurer.

* Apache Design Solutions announced it has been named in the top 15 of Deloitte's Technology Fast 50 Program, described as “a ranking of the fastest-growing software and IT companies in the Silicon Valley.”

* ARC International announced that “one of the top 10 SoC design companies in Taiwan” has taken an ARC license. Per the Press Release: “The new customer is incorporating ARC’s low power solution into cellular baseband designs targeting the worldwide cellular handset market. The company chose ARC IP because it could custom tailor the performance, while achieving the small size and battery efficiency demanded of chips servicing the growing global handset market.”

* ARM announced IP library support for IBM’s newly announced 45-nanometer SOI foundry offering. I spoke with Tom Lantzsch, Senior VP for the ARM Physical IP Division, on November 14th about the ARM announcement. Lantzch said ARM sees six focus areas wherein the SOI news is critical:

1) A market-timing point of view where today’s consumer content is focused on supporting content for the home and/or back office; 2) SOI can now be used at different performance levels and now addresses previous price/performance versus bulk production concerns; 3) SOI no longer lags bulk technology process nodes; 4) Having open foundry availability to 45-nanometer SOI will stimulate product growth in many sectors; 5) ARM’s library offerings that support IBM’s announcement means reduced barriers for those in the design community who want to work in this technology; and 6) There are now 20+ members in the ARM-sponsored SOI Consortium, spanning everyone from end-users to substrate providers. If there are unique tools needed for SOI design, they will be emerging from efforts out of that consortium.

* ASSET announced it has joined Synopsys' in-Sync program for third-party suppliers of EDA-related products. ASSET VP Alan Sguigna is quoted: "As the need for embedded instrumentation becomes more acute in the industry, it is incumbent upon us to support and interoperate with those tools that chip designers are using to insert this instrumentation. Then chip and circuit board designers, manufacturing engineers and even field service personnel will be able to use ScanWorks to access, automate and analyze embedded instrumentation throughout a system's entire lifecycle."

* Berkeley Design Automation announced what it calls “the industry's first closed-loop noise analysis of fractional-N PLLs at the transistor level. Combining transient noise and periodic noise analysis in the company's Noise Analysis Option device noise analyzer, designers can now optimize and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication. The result is improved performance, lower power, and faster time-to-market.”

* Cadence announced an expansion of its the ActiveParts Portal will now offer PCB design teams “greater access to key component information.” The company says it is working with Supply Frame, Inc. “to provide engineers with new choices and even greater access to the component information they need to create their designs.

In addition, Cadence announced new enhancements for the company’s OrCAD Capture CIS and Allegro Design Entry CIS products. Per the Press Release: “Technology and enhancements introduced for the OrCAD Capture CIS and Allegro Design Entry CIS products include a new capability called Context-aware Non-Linear Graphic Editing. The capability is a new schematic editing technology for dense designs that provides a magnifying auto-zoom between focus points during editing operations.”

* Calypto Design Systems announced a new version of its SLEC verification tool; supports fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing SoC devices. Calypto CEO Tom Sandoval is quoted: “Calypto has added new capabilities to comprehensively verify the latest high-level synthesis features.”

Calypto also recently announced Pixim used Calypto’s PowerProCG to significantly reduce power consumption in a new Pixim video imaging processor. Calypto also announced a collaboration with Forte on a SystemC verification and implementation design flow for consumer and multimedia products.

* Carbon Design Systems announced volume shipments of it SoC Designer. Recall that: “Carbon assumed development, support and sales of SoC Designer from ARM in July 2008, and now offers a complete system validation solution with cycle-accurate system modeling, cycle-optimized platform creation, execution and analysis, and cycle-accurate model kits for ARM IP.”

* CAST announced that 40 CASTcores have undergone evaluation and testing using Mentor Graphics Precision Synthesis FPGA tool. Daniel Platzker, Mentor Graphics FPGA synthesis product line director, is quoted: “After working with CAST on these cores, we’re happy to recommend them to our mutual customers for use with Precision Synthesis as part of our comprehensive, vendor-independent FPGA design flow.”

* Ciranova has chosen the excellent Eric Filseth to lead the company as CEO. Given that EDA legends Jim Solomon, Jim Hogan, and Ed Petrus are all on the Board of Directors (Petrus is also Ciranova COO), you will definitely be hearing big things from this company going forward. Stay tuned!

* congatec AG announced its conga-QA computer module based on the Qseven form factor (standardized form factor of 70mm x 70mm). It’s “fitted with the latest Intel Atom Z5xx range of processors and US15W system controller hub. Note this from the congatec: “The Qseven platform was specially developed with an eye on the latest low power processor technology and demand for small physical size.”

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