The Semiconductor Industry's Trusted IP Partner
Welcome to the October 2008 issue of IP Times – your continuing source for semiconductor Intellectual Property (IP) news, trends, and developments. Find out about Virage Logic’s latest news and upcoming events here first.
System-Level Design Portal:
Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 – White Paper
Check out the new System-Level Design Community web portal to read this informative white paper from Virage Logic. Learn about key design considerations when migrating to a DDR3 system interface from a DDR2 interface. Read the white paper.
Last Chance to Register! STAR™ Memory System Class – November 4-5, 2008
Sign up today for this extensive two-day course featuring lectures, hands-on tutorials, and labs that instruct you on how to integrate the STAR Memory System into your System-on-Chip (SoC) designs and accelerate your silicon success. STAR Memory System customers have improved yields by up to 250%, so don’t miss this opportunity to learn how you can effectively implement this solution to help increase yields. Also, don’t forget that the latest release of the STAR Memory System features an open memory interface to give designers the freedom to use the system's capabilities with their choice of Virage Logic memories, other commercially available third-party memories or internally developed embedded memories. The registration deadline is October 30th. Sign up now.
Virage Logic in the News
Virage Logic Announces Promotion of Dr. Alex Shubat to CEO
Recently the company announced the promotion of Alex Shubat, Ph.D., from chief operating officer (COO) to president and chief executive officer (CEO), and the appointment of J. Daniel McCranie, from chairman to executive chairman. Dr. Shubat takes over his new responsibilities from Mr. McCranie who, in addition to serving as chairman, also served as president and CEO. These two key executive management appointments will help facilitate the next phase of the company's product, market and economic transformation. Read more.
– Dr. Yervant Zorian, VP & Chief Scientist
View this new video featuring Virage Logic’s Dr. Yervant Zorian, one of the industry’s foremost technologists on embedded test and repair, to learn what he has to say about infrastructure IP to ensure the health of your chips. View the video.
– Brani Buric, EVP Marketing
Virage Logic’s Brani Buric is featured in this new video talking about the changes in system-level design in terms of escalating complexity and costs. View the video.
Open STAR Memory System Solution – Helps Customers Ramp to Volume Production
Virage Logic’s STAR Memory System features an open memory interface, giving SoC designers the freedom to use the system's capabilities with their choice of Virage Logic memories, other commercially available third-party memories or internally developed embedded memories. Leading IDM companies have used this open solution with their internally developed memories to ramp up to volume production at advanced process nodes. The STAR Memory System, when used in conjunction with the STAR™ Yield Accelerator, provides a complete RTL to test floor embedded memory test and repair solution, addressing the needs of SoC designers, test, and product engineers. Created to reduce time-to-tapeout and accelerate time-to-volume, the STAR Yield Accelerator bridges the design and manufacturing gap to enable automated test vector generation, silicon debug, fault isolation and classification to use for critical semiconductor characterization, bring-up, volume manufacturing, and electrical failure analysis stages.
Upcoming VIP Partner Events
Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.
Power Design Solution Techtorials - Canada
October 28, 2008
Hilton Suites-Markham, Markham, Ontario, Canada
October 30, 2008
Brookstreet Hotel, Ottawa, Ontario, Canada
Explore your options for managing power throughout the entire design process, get methodology recommendations and learn how you can effectively deploy such methodologies in your design environment.Cadence is hosting these free one-day Low-Power Design Solution techtorials to share best practices and proven capabilities. Virage Logic will be featured presenting, "Minimizing Design Complexity with Power-Optimized Physical IP." Come and discuss your low-power needs with a Virage Logic IP expert. Learn more.
CDNLive! – Israel
November 4, 2008
Avenue Convention & Events Center, Airport City, Israel
CDNLive! is a unique opportunity to network with industry experts such as the Virage Logic IP team, and to share your successes with other power users of Cadence technology. Come and learn about solutions to address your specific design challenges. Register to attend.
SMIC 2008 Technology Symposium – Japan
November 18, 2008
Shinagawa Conference Center, Tokyo, Japan
This symposium is for SMIC customers, IC designers, design service providers, packaging, assembly and test engineers, quality and reliability engineers, equipment and material suppliers, universities and research institutes. As long time partners with SMIC, Virage Logic’s IP experts will be on hand to discuss how we work together to provide a variety of System-on-Chip (SoC) solutions to meet your design needs. More information.
Upcoming Industry Events
As the industry’s trusted semiconductor IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today.
International Test Conference (ITC)
October 26-31, 2008
Santa Clara Convention Center, Santa Clara, CA
ITC attendees will learn how Virage Logic’s STAR Memory System features an open memory interface to give designers the freedom to use the system's capabilities with their choice of Virage Logic memories, other commercially available third-party memories or internally developed embedded memories. Virage Logic’s Dr. Yervant Zorian, VP and Chief Scientist, will host several informative tutorials and workshops during ITC. Come and meet Dr. Zorian and the Virage Logic IP experts to learn how our advanced technology can improve your yield. Learn more.
CSIA-ICCAD Annual Conference
October 28-29, 2008
Beijing International Convention Center, Beijing, China
This conference will focus on IC design, independent innovation, and collaboration as China’s IC design industry advances through interaction in the design chain. Hear Virage Logic speak on "Non-Volatile Memory on Standard CMOS Processes & Advanced DDR Controller Solutions Enable Cost-Effective Ultra-Low-Power Consumer Applications." Register to attend.
System-on-Chip (SoC) Conference
November 5-6, 2008
Radisson Hotel, Newport Beach, California
Attend the conference, workshops, and exhibits at the 6th annual SoC Conference. The Virage Logic IP experts will be exhibiting at the conference and the company will also be featured presenting, "Using Data Traffic Efficiency Metrics to Select the Best DDR Memory Controller for your Design." Click here for a free conference pass. or Register now.