Elastix Clocks Reduce Margins. Landing in Barcelona.

What is the approach that Elastix is using?
Our technology is based upon the concept of elastic clocks. We implement the global clocking network in the design so that the clocks become elastic and flexible in that it tracks the performance of the design. If the data path happens to be fast because the temperature is low, if it happens to be slow because it is on the slow part of the chip or because the voltage is low for some period, then the clock automatically tracks the data path. The clock is slow or fast depending upon the data path. By virtue of the clock tracking the data path, I do not have to make the clock slower than the worst the data can ever be.

So it is dynamically doing this?
It is happening live, dynamically. The advantage of all of this is that you can take any average block in the design, change the voltage of that block or any portion of that block. The design is still guaranteed to work but the performance is going to resonate with how you play with the voltage for example. All this is happening dynamically.

When you are verifying the chip, how do you know that this is in fact what is going to happen?
Good question. There are various verification aspects. One is verifying the design itself, that the design works and is correct. The nice thing about our approach is that it fits into existing design flows. We use the same standard RTL to GDSII flows, the same place and route, the same timing and functional verification. It is exactly the same RTL verification. That has not been touched. There is a problem of functional verification. We have altered the design. We have introduced some new circuit elements into the design. You have to verify that. The original circuit is a thing of the past. You use functional verification and certain tools from companies like Cadence and Synopsys. The results from timing verification is to verify that indeed at the corners the design still works and provides the performance you want. That is verified through sign-off, multicorner sign-off using standard timing verification tools, signoffs tools from Synopsys for example. The signoff is done at all the corners of the process, voltage and temperature.

Does the design get to some point of verification and then does your technology enter the picture? Is it a sequential process? The designer does some design or some design block, verifies that design, arrives at some comfort level and then brings in your technology (elastic clocks) and re-verifies.
Yeah, kind of. You have some design in your mind, some conceptual level, some system level. At some point you write the RTL for that design. You go through standard verification using whatever simulator you have. We do not come in until later. Then you synthesize the design using Cadence, Synopsys or Magma tools. Once the design is synthesized and is at the gate level, you are inserting the clock tree. That is where we come in. You apply the Elastix transformation. After applying that you get back into the standard design flow, physical synthesis and routing. You can do the verification immediately after applying the Elastic transformation as well as at all the subsequent stages.

We start from a pre-verified design and then we make any changes through our tools. We re-verify the impact of those changes though timing and functional verification.

Do you have any customers or beta sites for this technology?
Yes there are customers. We are working with some strategic customers who are checking out their designs. I am not in a position to disclose their names but we are working with several customers.

Have you set a potential price point for the product?
No. Actually we have not released the details of our product except to some customers. This will come in a few months.

Is there a particular set of end user applications for which this technology would have maximum benefit?
First it works for all designs but the sweet spot for this technology are designs which are system-on-chip where potentially you will be putting together blocks from different sources, from inside the company or from third parties. A lot of the time the devices are working for multiple applications. The chip that is in your cell phone is sometimes used for videos, sometimes for email and some times for simply talking on the phone. So you have different workload requirements. There are different voltage requirements under different workloads. Different blocks scale and perform differently. You need to be able to support different power and voltage requirements when blocks behave differently. So that is the perfect sweet spot for elastic clocks.

Another sweet spot is multicore applications where people are building multiple ports putting them together on the same chip whether it is a graphics chip, a simple process or router chip. They are putting many different ports onto the same chip and connecting them together. Any applications where you are putting multiple blocks together designed under different conditions and requirements and having to talk with each other and be interconnected and you have some flexibility in the connect in terms of the work requirements and variation. So low power applications.

How large a company is Elastix today?
We are about 10 people.

Do you envision selling directly or through distributors?
It depends upon the market. Initially we will be selling directly but as we go to Asia we will work with distributors.

Do you have a time frame for releasing the product?
In a few months.

Possibly at DAC?
No. We will not release before DAC. We are working with customers who have our product and are using it on their designs. We do not have an availability date at this time.

To your knowledge is there any other firm out there doing something similar?
There has been a lot of research in voltage scaling as well as making clocks flexible or less rigid. In terms of voltage scaling techniques there are a lot of in-house solutions in different places. They have to do with adaptive voltage scaling as well as dynamic voltage or frequency scaling where they are changing the voltage as the frequency of the block changes. But all of them are in the context of rigid clocks. Then in terms of changing clocks, there have been a lot of work in different segments. In the context of synchronicity and rigid clocks there have been efforts in implementing useful skew. There have been efforts in taking into account of on chip variation also called OCV. Then what we are doing is making the clock even more flexible than all of that. There are other companies that have taken radically different approaches like Handshake Solutions. Our approach is significantly different than that.

Why is your approach more effective than the more popular or traditional voltage scaling approach?
It is not that we are competing with any of the voltage scaling approaches. The issue is that we are able to exploit the voltage scaling. We can make voltage scaling as flexible as you want. You can make it at as fine a granularity as you want to make it. With voltage scaling today you are limited to scaling the voltage and scaling the frequency and doing some tight synchronization between the two steps but in doing that you are losing a lot of margin and you have to go back to voltage specific areas. In our technology you can scale voltage independently on any portion of the design or any sub-block you choose to. It is the most flexible way of voltage scaling.

Is it conceivable that a design could be so poor that you could not make it work, close timing even with elastic clocks?
I can not think of something like that. Are you saying that the design can not be made to work even in a synchronized rigid clock world?

Let me rephrase the question. Is it a prerequisite to using your technology that a design works first in a rigid clock world?
Yeah. It depends on what you mean. You can have designs with rigid clocks that do not meet your timing or power requirements and by using our technology you can get the design to meet those requirements. So a design that was not working in some sense is now working. If you had a design that was working, it will always work because with elastic clocks you can get additional benefits. You have to use the tool and get the results from the tool and the clocks become elastic. But if the design was working, it will always work at least at the same speed and power as before but typically much faster and at lower power than before.

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