Step-by-Step Functional Verification with SystemVerilog and OVM provides a complete guide and reference for adopting an effective functional verification methodology, learning the SystemVerilog language, and using SystemVerilog and the OVM library for building a verification environment for a realistic design example. With more than 500 pages of original technical content, none of which duplicates the documentation already available on OVM World, the book is unprecedented in both the breadth and depth of its information on advanced verification.
“Dr. Iman brings together all the essential elements to understand the use and application of the OVM,” said Dennis Brophy, director of Strategic Business Development at Mentor Graphics. “This book has everything design and verification engineers would want to know to apply the OVM to their most pressing challenges.”
“The OVM is one of the most quickly and widely adopted new solutions ever for verifying complex chips,” said Ted Vucurevich, CTO at Cadence. “This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of this book and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers.”
“This book fulfills the need for education in two critical areas: SystemVerilog verification and the OVM,” said James Baldwin, Staff Verification Engineer at Qualcomm Incorporated. “The blending of these topics in a single book provides a unique and efficient source for any verification engineer who wants to rapidly learn these leading-edge concepts and put them to use with a solid understanding.”
“There is significant industry interest in the OVM but it can be difficult figuring out how to get started,” said J.L. Gray, owner of the popular and influential Cool Verification blog ( www.coolverification.com) and an Associate Principal with Verilab, Inc. “Dr. Iman's book provides a solid introduction to the OVM and includes a set of helpful examples demonstrating key concepts related to sequences, factories and configuration constructs. It's definitely a must-read for engineers building testbenches with the OVM.”
Step-by-Step Functional Verification with SystemVerilog and OVM is now available for ordering at either of the following sites:
Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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