Buzz@DAC & Kuhl@CAL
Director of Technical & Product Marketing
Berkeley Design Automation
* Calypto Design Systems will distribute free copies of its PowerPro-filer that calculates Clock-Gating Efficiency and the percentage of registers clock gated in an RTL design block. Clock-Gating Efficiency measures the percentage of time a register is gated (turned off) for a given set of activity vectors making it a better indicator of dynamic power savings.
Director of Product Marketing
Calypto Design Systems
* Pyxis Technology will demonstrate NexusRoute at DAC, and feature a customer video outlining why NexusRoute was named one of EDN’s Hot 100 Products for 2007. Visit our booth or catch the Exhibitor’s Forum on June 11th at 9:15 am to hear about how Pyxis helped customers like Microsoft achieve faster design closure, better performance, and lower power. While you are there, signup for a chance to win your own copy of Guitar Hero III.
Vice President of Marketing
Pyxis Technology, Inc.
* Tela Innovations will be showing its solution for the 'sub-wavelength,' low-k1 era – 45 nanometers and beyond. The Tela solution uses gridded, straight-line, one-dimensional layout structures to produce a lithography-optimized layout. It is applicable for use in logic, embedded memory, analog, and I/O functions. The result of using Tela's pre-defined, predictable topologies is significant improvements in variability, performance, leakage and area. The solution is complementary to existing SoC design flows using synthesis and conventional cell-based design methodologies.
Vice President of Marketing
* In April 2008, Envis announced its mission to dramatically reduce power for SoC designs, automatically! Chill, an intelligent, push-button solution for both dynamic and static power reduction, is based on unique, proprietary clock-gating technology. Envis also announced Kelvin, an automatic power pattern generation (APPG) solution. Visit Envis at DAC 2008 and see what’s cool in power reduction!
* Unlike coverage-driven RTL verification, OneSpin’s recently-announced GapFreeVerification process ensures error-free digital modules and IP – and considerably reduces verification effort. At DAC 2008, we’ll show visitors how. We’ll also present how our 360 Module Verifier supports formal SystemVerilog assertion-based verification, using both new and legacy assertions. Most important, we’ll be showing our latest, yet-to-be-announced breakthrough in formal RTL verification.
* DAFCA will be showing ClearBlue at DAC, which accelerates and automates hardware-software validation. Our on-chip instruments are seamlessly inserted pre-silicon and configured, operated, and controlled post-silicon with a comprehensive set of analysis and stimulation tools. They can also be accessed by system and application software. ClearBlue is used in simulation, emulation, and FPGA-prototype environments – in addition to final silicon – and doesn’t require special pins or cell libraries.
President & CEO
* Liga Systems will be demonstrating NitroSIM v1.0 – the 1st release of our hybrid simulation technology that accelerates functional Verilog simulation by 10x. The technology has matured in half a dozen beta sites for one-and-a-half years in applications such as graphics processors for video game industry, networking, and broadband digital broadcasting in single chip to multi-chip verification projects. Visit us in our booth at DAC.
Director of Technical Marketing
* Jasper Design Automation delivers Formal Verification Unleashed – an advanced verification methodology for complex designs from architecture to silicon for: designing, exploring and debugging RTL; verification of block-level functionality; comprehensive regression testing; and fast silicon validation and debug. Jasper's high-capacity, high-performance formal verification uniquely delivers benefits across the design flow. Visit Jasper in our booth at DAC.
Jasper Design Automation
* Real Intent is showing verification tools powered by formal analysis technology. This includes Ascent all-in-one automatic verification with its new combined LINT and automatic formal analysis, Meridian CDC (Clock Domain Crossing) analysis software, the leading formal powered clock analysis tool for verifying clock domain crossing design and PureTime for verifying Synopsys Design Constraints (SDC) false and multicycle paths with fully sequential accuracy.
Vice President of Marketing & Business Development
* Please come to the Silicon Canvas booth, to see how our Laker custom IC design solutions make better chips with less effort. Our demos feature Laker’s automated custom layout tools with our drag-and-drop schematic-driven layout flow, as well as constraint-driven custom placers and custom routers, including our new matching device solution. We are also showing Laker interoperability and run-time model integration with OpenAccess.
Director of Marketing
* Breker Verification Systems knows chip designers are concerned with the outputs derived from circuit functionality. Iterating and tweaking constrained random test case generators to define input transitions is no longer an efficient way to accomplish functional verification goals. One approach that’s gained momentum is “coverage model-driven scenario generation” technology that defines the verification space and automates input stimulus generation based upon design outcomes. A coverage model approach works best and gives the highest percentage coverage when combined with graph-based GUI technology. How does a graph-based GUI work in functional verification? Come visit us in our booth at DAC and find out.
Vice President of Marketing
Breker Verification Systems
* Virage Logic will be featuring its recently introduced 40-nanometer SiWare memory compilers and logic libraries that enable SoCs to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields. We will also be featuring our Intelli DDR solution, an all-digital implementation including the PHY and DLL that delivers smaller area, lower power, and significantly easier portability to any process node for any foundry. Come visit Virage in our booth at DAC.
Vice President of Corporate Marketing
* XYALIS provides advanced solutions for layout finishing and mask-data preparation. At DAC 2008, XYALIS will release a unique mask-data management flow including support for 1X Masks, Multi-Layer Reticles, and Wafer Plan, as part of our production-proven GTmuch and GTframe tools. XYALIS presents enhancements to its metal-filling solution, GTstyle, to further improve the yield of 90-nanometer, 65-nanometer, and 45-nanometer designs.
* IMEC advances state-of-the-art technology by joining process technology and design methodologies, housing process and design technology under one roof, and working to bring the industry up-to-speed for designing in the newest technologies. IMEC's technology-aware design research pursues analysis and design solutions for sub-45-nanometer scaling-induced problems that can be compensated at the system level. The focus is on variability- and reliability-aware modeling, as well as ways to cope with their effects at the system level. IMEC's multi-processor system-on-chip research focuses on tools that assist software developers to distribute applications over multiple processors, whilst handling task-synchronization and inter-task data exchange. IMEC's unique Clean C code style and toolbox increase the efficiency of mapping sequential C on multi- and many-core platforms.
Technical Business Director
Nomadic Embedded Systems Division
* IC designers face extreme challenges with time-to-market pressures, and the need to rapidly reduce cost and re-use as much as possible. Synfora, the premier provider of algorithmic synthesis tools used to design complex SoCs and FPGAs will be highlighting our PICO Extreme solutions at DAC this year. PICO Extreme solutions deliver the best results faster -- including lower power from state-of-the-art algorithms and 20-50 percent reduction in cost, along with low risk step-by-step deployment. Synfora will also be presenting our solutions at various workshops at DAC. Visit our website to explore our presentation schedule.
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