Accellera's TSCs produce effective and efficient standards for today's advanced IC designs. Participation comes from Accellera member companies and independent industry contributors. Technical contributors typically have many years of practical experience with IC design and developing and using design automation tools.
"Accellera is very proud of the achievements and excellence of its Technical Committee chairs," said Shrenik Mehta, Accellera Chair. "Karen Pieper has the valuable experience and the leadership abilities to drive the development of multiple standards through both the Accellera and IEEE processes."
"Accellera has proved itself to be an invaluable organization for improving the electronic design industry, and I am pleased to be leading the technical subcommittees that are major contributors to the continued success and adoption of Accellera's electronic design standards," added Karen Pieper.
Karen Pieper is currently Director of Synthesis at Tabula, and was formerly Director of Synthesis at Synopsys. She is currently serving as the Chair of the IEEE 1800 SystemVerilog Working Group, an Accellera-sponsored committee and has served as Accellera's TC Co-Chair and Co-Chair of Accellera's SystemVerilog-Basic Committee (SV-BC), the committee responsible for IEEE 1364 comments and basic extensions. In 2005, along with Johny Srouji, Karen was a recipient of Accellera's Technical Excellence Award. The Award recognizes major contributions to the development of Accellera's standards by Accellera's technical committee members. Award information is located at www.accellera.org/award.html.
Karen has a Bachelors degree in Computer Science from Rice University, and a PhD. in Computer Science from Stanford University.
Accellera's Technical Subcommittees
Accellera's current Technical Subcommittees include: Interface (ITC), Open Compression Interface (OCI), Open Verification Language (OVL), Property Specification Standard (PSL), SystemVerilog, Unified Coverage Interoperability (UCI), Unified Power Format (UPF), Verilog Analog/Mixed-Signal (Verilog-AMS), Verification Intellectual Property and VHDL. More information is at www.accellera.org.
About Accellera's Electronic Design Standards
Accellera has transferred its completed standards work to the IEEE and continues to use this strategy as part of the roadmap for all of its standards.
To date, seven Accellera EDA standards have been ratified by the Institute of Electrical and Electronics Engineers (IEEE) -- Hardware Description Language (HDL) standards, Verilog or IEEE 1364, VHDL or IEEE1076, Property Specification Language (PSL) or IEEE 1850 and SystemVerilog or IEEE 1800; Standard Delay Format (SDF) or IEEE 1497; Delay and Power Calculation System (DPCS) or IEEE 1481 and Advanced Library Format (ALF) or IEEE 1603. In addition, two standards are active in IEEE working groups, Open Compression Interface (OCI) or IEEE 1718, and Unified Power Format (UPF) or IEEE P1801. Accellera's most recent advanced design and verification language standards include the SystemVerilog and the Property Specification Language (PSL) standards.
Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control.
For more information about Accellera, please visit www.accellera.org.
Notes to editors: A photo of Karen Pieper is available on request. All trademarks and tradenames are the property of their respective holders.
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