De Micheli suggested the tasks he laid out were not easy, but that complex, multi-variate systems could and should be designed. The results, he said, will “expand our horizons and [increase our] commercial viability. EDA vendors need to keep the faith, look at things from a systems perspective, and realize that most of the potential of the technology is still untapped.”
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Vernay invoked Moore’s law, raised the specter of two major hardware challenges – reduced footprint and increased parallel processing – and laid out a 10-year road map for embedded systems. He said further implementation of embedded systems in mission critical applications would depend on adhering to the roadmap, and noted that additional industry standards, as well as correct-by-construction design techniques were also crucial. No one in the audience took issue with his closing message: We must educate under the “Systems” banner and learn to engineer for uncertainty!
Next, I rushed to the EDAC/Synopsys organized panel on ESL. Having moderated a couple of panels in this topic area myself over the last several years, and having attended even more as an observer, I’m beginning to believe quite honestly that this material has been hashed over too many times in a panel venue.
Having said that, Mentor Graphic’s Simon Bloch moderated a lively discussion between Infineon’s Wolfgang Ecker, TU Braunschweig’s Rolf Ernst, Synopsys’ Joachim Kunkel, Ericsson’s Peter Nord, The MathWorks’ Ken Karnofsky, and Altera’s Misha Buric. Bloch asked if there’s a definition for ESL. Kunkel said no, while Karnofsky, Ernst, Buric, Nord, and Ecker all said yes, but with a host of qualifications. My two take-aways from this session: Implement ESL and harvest the benefits; and there’s a Peter Principle in ESL. The next level above the current level of design abstraction is always the one that should drive the specifications. Oh yeah, two more things: There are more software designers in the world than hardware designers, and the gap’s increasing; and by 2010 there will be 100 million lines of code residing in your average automobile.
I left the ESL panel early to catch the final talk in Session 1.7, presented by Srinivasan Murali, and learned a bit about an EPFL research project: “A method for temperature controlled dynamic frequency scaling of multi-core systems.” Pretty interesting stuff requiring further reading, but the uber-lesson was clear: Multi-core systems dissipate a lot of heat in a non-uniform kind of way, creating hot spots on-chip. Novel, innovative solutions must be developed if such systems are to realize their full potential, particularly in embedded, mobile applications.
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IMEC researchers have developed a set of 28 guidelines and restrictions which C programmers can use to help nudge their code into some sort of parallizable structure. Lauwereins and others believe it will go a long way towards alleviating the daunting challenge of producing C code that can actually take advantage of the multi-core megaliths the hardware world is pumping out.
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Next, I arrived late for the Rich Wallace (EE Times) moderated panel: “From IDM to Fab-lite: Changes in your EDA Strategy.” As the bulk of the semiconductor companies in Europe have shed their manufacturing capability of late, this discussion had particular currency. NXP’s Barry Dennington said, “A strong affiliation with a foundry partner ecosystem is mandatory, [along with] eliminating duplicated activities such as internal tool development and multiple flows.”
When pressed by Wallace, Dennington replied, however, “ Any organization that understands how the tools work together and has the capability of tying together those tools could be a partner to the design house. It could be the foundry, or it could be other companies who manufacture the products, or have a service business and want to step into the design flow.”
Wow. Scary stuff, if you’re an EDA vendor. Or, exhilarating if you’re a TSMC. A question from the floor made the same point: “The center of gravity in the semiconductor business is moving towards the TSMCs of the world, companies that are strongly involved in manufacturing, but also have efficient and complete design flows. Add to that, the fact that there are a bunch of designers coming online just across the Straights of Taiwan. Can you comment?”
Domic replied, insisting that reference flows – TSMC’s 8.0, for example – are not design flows, plus the foundries still rely heavily on the big EDA vendors for input. The Questioner replied, “Yes, but they’re working at 45 nanometers, they’ve already instituted statistical timing analysis, and they’re very advanced.” Domic was unperturbed: “The TSMC flows are based on Synopsys, Cadence, or maybe Magma, and it’s still a non-trivial step from a reference flow to a design flow.”