Silicon Logic Engineering Launches High Performance Interlaken Interconnect Protocol Core
SLE's new Interlaken IP Core is now available with more than twice the performance of the standard 60Gb/s version. This new high-speed core delivers the performance and bandwidth that new designs require, now with higher data transfer rates. The higher performance Interlaken Core is fully scalable, ideally suited for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24).
SLE is currently shipping the new 150Gb/s core, and customers report that the IP delivers the highest data transfer rates available on the market today. "SLE continues to bring innovative, industry-first technology to market" said Jeff West, Vice President of Design Services, SLE - a division of Tundra Semiconductor. "Tundra's customers have come to rely on the quality and reliability of SLE's custom design services and IP core development."
Designed and tested to be easily synthesizable into any ASIC technology, SLE's Interlaken IP Core was built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.
"Tundra is committed to delivering outstanding design services and quality IP to customers. SLE continues to demonstrate our commitment to world-class design and development and Tier 1 customer response to this enhanced Interlaken core demonstrates strong market acceptance of this first-to-market IP offering," said Daniel Hoste, President and Chief Executive Officer, Tundra Semiconductor.
The SLE licensable 150 Gigabit Interlaken IP is available through SLE's sales network. For sales related questions, contact sales at Email Contact or call SLE at 1-908-580-1870.
About Silicon Logic Engineering
Silicon Logic Engineering, Inc. (SLE) specializes in right-first-time design services that address all aspects of ASIC, FPGA and semiconductor system design services. SLE's proven and repeatable Think Physical(TM) design process, tools and semiconductor intellectual property reduce time-to-market and are provided by one of the most experienced VLSI design services teams in the industry. SLE is a division of Tundra Semiconductor Corporation . For more information about SLE, please visit http://www.siliconlogic.com.
Tundra Semiconductor Corporation supplies the world's leading communications, computing and storage companies with smart System Interconnect products and design services backed by world-class customer service and technical support. Tundra's track record of product leadership includes over a decade of bridges and switches enabling key industry standards: RapidIO(R), PCI, PCI-X, PCI Express(R), Power Architecture(TM), VME, HyperTransport(TM), Interlaken, and SPI4.2. Tundra's products deliver high functional quality and simplified board design and layout, with specific focus on system level signal integrity. Tundra's smart System Interconnect products connect critical components in high performance embedded systems around the world. For more information, please visit www.tundra.com.
SLE, the SLE logo and Think Physical are trademarks of Silicon Logic Engineering, Inc.
TUNDRA is a registered trademark of Tundra Semiconductor Corporation (Canada, U.S. and U.K.). TUNDRA and the Tundra logo are registered marks of Tundra Semiconductor Corporation in Canada, European Union, People's Republic of China and the United States. Design.Connect.Go. is a trademark of Tundra Semiconductor Corporation. Other registered and unregistered trademarks are the property of their respective owners.
(C) Copyright 2008 Silicon Logic Engineering, Inc. All rights reserved. Information subject to change without notice. Definitions: ASIC: Application Specific Integrated Circuit High-End ASICs: 90nm or smaller technology, 30 million or more logic gates, with or without challenging power requirements. FPGA: Field Programmable Gate Array I/O Pins: Input and Output Pins IP: Intellectual Property. This news release refers to licensable ASIC or FPGA blocks of intellectual property. Interlaken: An ultra-scalable chip-to-chip interface protocol written as an open specification by Cortina Systems and Cisco Systems, developed as licensable ASIC and FPGA IP by SLE. SERDES: A SERDES (serializer/deserializer) transceiver converts parallel data to and from serial data, thereby reducing the number of signals needed in a chip to chip interface. SPI4.2: The System Packet Interface Level 4 Phase 2 is a high-speed interconnection for 10Gbps aggregate bandwidth applications. The SPI4.2 standard was written by the Optical Internetworking Forum http://www.oiforum.com. The SPI4.2 is also abbreviated as SPI-4.2, SPI-4 Phase 2 and SPI Level 4 Phase 2. VLSI: Very Large Scale Integration XAUI: A chip-to-chip interconnect using four lanes of 3.125Gbps serial data. XAUI is defined by IEEE802.3ae and used in 10 Gigabit Ethernet (10GbE) systems.