Does the Industry Need Another P&R System?



Introduction

Does the industry need yet another place and route system? This is the question that Eric Thune asked himself and others before joining ATopTech as VP of Sales and Marketing. He obviously answered the question with a yes. He would undoubtedly say the industry needs not only another P&R system but a better one. I had an opportunity to discuss this with him recently.

Would you give us a brief biography?
I got my start as an electrical engineer, a design engineer for about five years. Then I moved into the sales and marketing area at Texas Instruments. I worked there for a number of years and moved on to the EDA world at Synopsys. After that I was the first sales rep at Simplex Solutions. I was also the first sales rep at a company called Synchronicity that was in the EDA space. Previously to ATopTech I spent my last three years at Apache running the west coast sales for them.

How long have you been at ATopTech?
Almost 2 years.

What attracted you to ATopTech?
I talked with several of my customers that I had a good relationship with and asked them whether the world needed another place and route solution. I was actually surprised that the answer was a resounding yes. Even with the three or four solutions already in the market customers were not able to get their jobs done without a lot of pain. They said that the really needed someone to come in and deliver something that works at 65nm and below. This was not just one customer but many, many customers that I talked to. After doing that due diligence, it was extremely attractive. Then that combined with the talent that we have here and the track record of the team, it was a no-brainer at that point to come over here.

Would you give us some background on the company?
Some of the original people here trace their roots all the way back to Avanti, part of the original team that did the palace and route solution, Apollo, at Avanti which eventually became at Synopsys after the acquisition. We really have a mix of EDA people from across different companies. People from Cadence, people from Synopsys, people from Chips, and Verplex. We also have people from Magma. People from across the entire industry.

When was the company founded?
Four years ago in January 2004. The two founders were Dr. Don_Min Tsou who is our president, originally from Avanti and responsible for the Milkyway database for Synopsys, and Kaiwin Lee our executive officer whose background is also from Avanti and was most recently at Tera Systems. Later Ping-San Tzeng joined our company. He is a very well known router guru.

What was the market opportunity or problem to be solved that the founders saw?
What they saw generally in the market was that the EDA vendors lost focus on their place and route tools. They were off trying to create their next opportunities in things like DFM. We saw things like 90nm come along. These vendors kind of limped their way through but when the tools hit 65nm they really stumbled in a big way. The problem was that the design rules got much tougher. Signal integrity problems got much worse. These tools were architected in some case 10 years and even 15 years ago. They were never intended to solve these types of problems. What we see is that the current vendors kind of put patches on top of their tools to try to make them fix the problems we see today. They are really not doing that successfully. The other opportunity that we saw is that we now have hardware available with multiple CPUs very inexpensively. We really wanted to build a solution that would take advantage of these CPUs that are now available at inexpensive costs.

How large a company is ATopTech today?
We are just under 40 people.

When was the product first released?
The product was released in December 2006.


You released the product in December 2006 but your most recent press announcement suggests that you did not announce the release or make a big market splash at that time.
We did not announce the product back in 2006 when we first released it. We did make our announcement in 2007. The reason for doing that is that all too many times EDA companies make product announcements before they have customers and have revenue. There is really a lot of hype behind their product announcements. What we wanted to do is to announce our product when we had customers and revenue as well as tape-out success.

How many customers did you have during that year?
We are not releasing the number but there were several customers involved. We have actually done at this point close to 10 tape-outs already. That is probably going to go up by a factor of 5 or more this year.

The company is venture funded. How much has been invested to date in ATopTech?
We have raised a total of $14 million thus far. It was a combination of our founders and venture capital including Acorn Campus, id Innovation and Hambrecht and Quist.

Can you characterize the 10 tape-outs by process node, end applications and so forth?
There were several at 90nm and several at 65nm. We have 45nm to 40nm projects already going on. In reality we are very focused on the 65nm node and below.

How much revenue is the company generating?
We are already generating multiple millions in revenue.

How many millions?
I can’t disclose that.

Why another place and route solution?
I somewhat answered the question already. Let me go into more detail. At 180nm and 130nm what the industry saw was that wire load models are not accurate enough without placement information in order to get good results. The result is that we saw placement based synthesis. We saw things like physical compiler come about. At 95nm and 65nm we are seeing that crosstalk noise can not be accurately modeled without having real routing information. So the problem is that current tools are making very gross estimates of what the crosstalk noise is or just basically putting a margin on top of the constraint to try to accommodate that. So as I mentioned earlier at 65nm we saw the current generation of tools breaking down. The reason is that there are now challenges such as handling OCV (On Chip Variation), MCMM (multi-corner multi-mode) and very complex design rules. As a result of all this we saw the runtimes for these blocks exploding. DRCs became unfixable. Another big problem is that the timing out of the place and route tools does not correlate to the signoff tools. The physical designer might think his block is done, run it through sign off and find out that they have not only thousand of timing violations but they also have thousands of DRC violations as well. Timing closure became a manual task. We saw a lot of chips slip their schedule and I mean significant slippage. In the meantime the big EDA vendors were vigorously pushing their DFM solutions. That was not really answering the true problem designers were having.

Would you tell us about the new system?
ATopTech Aprisa is a complete netlist to GDS II design system. We do everything in terms of floor planning, placement, clock tree synthesis as well as normal routing and detailed routing. Aprisa solves today’s challenges. It solves the advanced design rules at 65nm and below. It takes advantage of sophisticated parallel processing and makes use of inexpensive multi-core CPUs for fast turn around time. We made it handle things like multi-corner, multi-mode, on chip variation. It has a very high capacity with a small footprint.

Where are a lot of tools that tap out at 3 or 4 hundred thousand instances, we are able to do blocks or chips of 2 million instances. If you saw the press release from Sharp they mentioned how they were able to do a design flat where the existing tool that they had had to do it hierarchically and they literally could not get the project done without using our tools.

Typical View of an Intermediate Timing/Optimization Result

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