Fireside Chat: Rick Lucier & Jim McCanny

“Our customers are always looking for ways to run their algorithms faster, so it was a great fit [between Celoxica and Catalytic]. We stayed [closely] involved with the situation at Celoxica, and as some of the other companies bought other parts of the company, we were able to put that part of the Celoxica product line together with the Catalytic product line to create a focus on algorithmic development and implementation. It’s pretty rare for a private company like Catalytic to get another product line as big and as established as Celoxica’s ESL product line. There are so many new applications [that come out of this move] and there are so many potential new customers, we’re very excited about all of this!”

* Xilinx announced that Moshe Gavrielov has been appointed President and CEO, succeeding Willem Roelandts, who will remain as Chairman of the Board. Per the Press Release: “Gavrielov will be the third Xilinx CEO in the company’s 24-year history, and brings 30 years of executive management and engineering experience with semiconductor and software companies to Xilinx. Most recently, Gavrielov served as Executive Vice President and General Manager of the Verification Division at Cadence Design Systems. Before that, Gavrielov spent seven years as CEO of Verisity, where he grew the company from a $4 million start-up, taking it through its IPO in 2001 to a $70 million publicly-traded company, and ultimately to its acquisition by Cadence in 2005.”

* SynTest announced that company founder Dr. L.-T. Wang has been named an IEEE Fellow. Per the Press Release: “Wang founded SynTest in January 1990. Since then, Dr. Wang has led the company to grow to more than 50 full-time employees and 200 customers worldwide. Along with overall management responsibility for worldwide operations, he is also responsible for defining SynTest's technology roadmap. Prior to founding SynTest, Dr. Wang had worked at several technology companies, including Intel and Daisy Systems. Dr. Wang has published more than 40 technical papers and currently holds 16 U.S. and European patents in the area of Test Generation, BIST, and DFT. He is also a co-editor and co-author of: VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007). He received his MSEE and EE PhD degrees from Stanford University, and his BSEE and MSEE from National Taiwan University, Taiwan.“

* Northrop Grumman Corp. announced a new “world record” for transistor speed with what the company says is “an ultra-fast device that will provide much higher frequency and bandwidth capabilities for future military communications, radar and intelligence applications.” Per the Press Release: “The company has produced and demonstrated an indium phosphide-based High Electron Mobility Transistor (InP HEMT) with a maximum frequency of operation of more than 1,000 gigahertz, or greater than one terahertz.” The Northrop results were showcased at IEDM in Washington, D.C., in December 2007.

* Samsung Electronics Co., Ltd. announced “the world’s fastest memory, a GDDR5 (series five, graphics double-data-rate memory) chip that can transfer data at six gigabits per second, which is more than four times faster than that of memories in state-of-the-art game consoles today.”

* X-FAB Silicon Foundries announced that the Brazilian-government-backed Excellence Center for Advanced Electronic Technology [CEITEC] has established a licensing agreement with X-FAB for semiconductor manufacturing. Per the Press Release: “CEITEC will license X-FAB’s advanced 0.6 micrometer process technology called XC06, enabling CEITEC to establish the first commercial CMOS semiconductor front-end manufacturing operation in Brazil … CEITEC is part of a Brazilian-government-sponsored effort to develop a domestic microelectronics industry … CEITEC’s 0.6 micrometer process will be fully compatible with X-FAB’s XC06 process.”

* IMEC says it is “setting foot in Taiwan.” Per the Press Release: “IMEC has officially established IMEC Taiwan in the Hsinchu Science Park. IMEC Taiwan initially starts as a representative office but is expected to grow into an R&D center within the coming 6 months. IMEC Taiwan aims to set up a win-win situation by facilitating the access for Taiwanese semiconductor companies to IMEC's R&D programs and tap into the local high technology skills … IMEC intends to reinforce its collaborations in Taiwan by focusing on semiconductor process technology research with foundries, on IC and system design with companies and academia, on dedicated training, on facilitating the interaction between Europractice IC service and the Taiwanese foundries for low-cost IC prototyping and small volume production, and on developing heterogeneous process technologies for fablite and fabless companies.”

* AtopTech was launched as a new EDA company and announced a product for the physical design of ICs at 90 nanometers and below. Per the Press Release: “ATopTech Inc., was formed in late 2003 and development on the EDA software was begun in 2004. The company has raised $14 million in two rounds of funding. Investors include the founding team, Acorn Campus Fund II, VCEDA, iD Innovation, Inc., and H&Q. Founders include Don-Min Tsou, President; and Kaiwin Lee, Executive Officer. Rounding out the executive team are Ping-San Tzeng, Chief Architect; Eric Thune, Vice President of Sales and Marketing; and Eddie Araki, President of ATopTech KK in Japan. Members of the Board of Directors are Don-Min Tsou, Kaiwin Lee, and Wu-fu Chen, managing member and co-founder of Acorn Campus.”

Do the Venn Diagram …

* Cadence Design Systems and Mentor Graphics announced the Open Verification Methodology (OVM). Per the Press Release: “Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from the OVM website.”

* Magma Design Automation, Mentor Graphics, and Synopsys announced the three companies are now delivering low power EDA tools based on the Accellera-developed Unified Power Format standard, UPF 1.0. Per the Press Release: “This includes a broad range of implementation and verification products from the three companies. This new UPF product support further enhances key low power capabilities in the companies' tools while expanding industry interoperability, especially when compared to other available options.”

* Cadence Design Systems announced that Japan's STARC [Semiconductor Technology Academic Research Center] released its “next-generation ultra low-power” PRIDE reference flow V1.5, that the organizations say incorporated the Common Power Format based on Cadence’s Low-Power Solution. Per the Press Release: “This reference flow also includes key litho-aware DFM technologies from Cadence.”

Additional recent news …

* Acceleware Corp. and Synopsys announced “a new hardware solution that enables up to 20-times faster electromagnetic simulation of optoelectronic devices such as CMOS image sensors.” Per the Press Release: “[The solution] links Synopsys' … TCAD Sentaurus Device simulation software and Acceleware's ClusterInABox Quad Q30 workstation, and enables an order-of-magnitude speed-up of the high accuracy finite-difference time-domain (FDTD) electromagnetic modeling algorithm used in Sentaurus Device.”

* ACE (Associated Compiler Experts) announced that ClearSpeed Technology used ACE’s CoSy compiler development system in the development of “a high-performance, parallelizing compiler for [ClearSpeed’s] accelerator product line that includes the CSX600, a multi-threaded array coprocessor … The CSX600 is a massively parallel processor architecture with a SIMD data path with 96 processing elements, each equipped with a dual 64-bit FPU, local registers and local memory.”

* Actel Corp. announced its Icicle Kit, which the company says leverages the Actel 5-microwatt IGLOO FPGA. Per the Press Release: “The $99 kit allows designers to easily and rapidly program, evaluate and modify their low-power IGLOO-based portable designs. Powered by a rechargeable lithium-ion battery, the 1.4” x 3.6” Icicle evaluation board consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone.”

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