Apache Design Plus Optimal Equals?

While many firms could possibly compete wit Apache, which ones do you see today as competitors?
Today, we compete will all the big vendors just like any other EDA solution provider. We compete with every one and we continue to execute. We have not lost any technical benchmarks in a long period of time. Out major customers continue to invest in Apcahe getting more license that are require for their next generation of design. That drives our consecutive record quarters. Our business is a strong indication of our competitive position in the market today. I believe that is the biggest endorsement.

What is the list price of the some of the various products?
We won’t give out that information for public access.

Would you like to expand on the capabilities of the second generation product under development?
No. We will spend more time in the near future to give more information about the second generation, its approaches and benefits but not on this call.

The top articles over the last two weeks as determined by the number of readers were:

Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling. The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry standard language for ESL design, today announced the milestone release of the new transaction-level modeling standard, TLM-2 draft 2. This standard enables model interoperability and reuse at the transaction level, providing an essential framework for ESL design. The public review period is now open to the worldwide SystemC community and ends on January 31, 2008. SystemC users, ESL tool developers and IP providers are encouraged to participate and provide feedback. The TLM-2 draft 2 kit is made available under open source license and includes a requirements specification, documentation, library and examples. To download, visit www.systemc.org.  

Real Intent Ships Next Generation of Ascent Automatic Verification Software, Finds Design Bugs Early Real Intent, Inc. announced that it is shipping a new version of its Ascent™ software for automatic formal verification of electronic designs. Ascent finds bugs in Register-Transfer-Level (RTL) designs and improves design quality, with significantly higher performance when compared to Real Intent's previous generation of automatic verification software, Implied Intent Verification. Ascent is shipping now, was first introduced in 2006, and replaces Real Intent's Implied Intent Verification software. The price starts at $35,000 for a one year term license. Existing customers on active maintenance receive Ascent at no charge.

Verigy Signs Agreement to Acquire Inovys announced that they have signed a definitive agreement for Verigy to acquire Inovys. Inovys, privately held, provides innovative solutions for design debug, failure analysis and yield acceleration for complex semiconductor devices and processes. Financial details were not disclosed. The acquisition is expected to be final in 30 to 60 days, subject to certain closing conditions.

ATopTech Signs Multi-year, Multi-million Dollar Contract with Broadcom ATopTech, Inc. announced that it has entered into a multi-million dollar per year, multi-year contract with Broadcom Corporation, a global leader in wired and wireless broadband communications semiconductors. Broadcom will use ATopTech's next generation place and route software for designing integrated circuits at 65nm and below. Broadcom's first chip using ATopTech's software has already taped-out and had first pass silicon success. On the same day ATopTech launched the company and unveiled a new product with new technology for the physical design of ICs at 90 nanometers and below. The company formed in late 2003 and development on the EDA software was begun in 2004. The company has raised $14 million in two rounds of funding. Investors include the founding team, Acorn Campus Fund II, VCEDA, iD Innovation, Inc., and H&Q.

Other EDA News

SiPort Selects Berkeley Design Automation Analog FastSPICE(TM) for Mobile Digital Multimedia Broadcast Receivers
Mentor Graphics Precision Synthesis Combined With Xilinx SmartGuide Technology Dramatically Reduces Design Time
UMC Releases 65nm DFM Design Enablement Kit
ATopTech Signs Multi-year, Multi-million Dollar Contract with Broadcom
Pioneers in Breakthrough IC Design Tools Launch New Company, Announce Proven Physical Design Product
Tensilica Enhances Xtensa Configurable Processor Families With New Options, Bridges and Software Tools
Virage Logic Partners with MTEK I&C to Bring Its Advanced Silicon Aware Intellectual Property (IP) to the Korean Design Community
Virage Logic and Marketech International Corporation (MIC) Partner to Provide Silicon Aware Intellectual Property (IP) to Rapidly Growing China, Singapore, and Taiwan Markets
OneSpin Solutions Delivers First Equivalence Checker Dedicated to FPGA Synthesis Verification
Mentor Graphics Announces Industry's First Multi-mode Multi-corner Signal Integrity Solution for 65/45nm

Other IP & SoC News

ON Semiconductor Releases New PureEdge(TM) High-Performance Clock Generation Devices for Telecom, Networking and Consumer Applications
Wind River Enhances On-Chip Debugging Solutions to Address Growing Complexities in Mobile and Handheld Device Development
Seoul Semiconductor Introduces the World's Thinnest High-Brightness Chip-LED at 0.17mm
Fresco Microchip Delivers High Performance, Low Power Single-Chip Hybrid Receiver for Terrestrial and Cable Television
UMC Releases 65nm DFM Design Enablement Kit
OKI Increases its Lineup of Power Management LSIs for Mobile Devices

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