Jasper Design Automation Hires Distinguished Formal Verification Expert Ziyad Hanna as Chief Architect and Vice President of Research

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—December 5, 2007— Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced it has hired prominent formal verification expert, Ziyad Hanna, to serve as chief architect and vice president of research. Prior to joining Jasper, Hanna was Intel senior principal engineer and the main leader of the Formal Technology Research and Development Group in the Design and Technology Solutions division at Intel Haifa. At Jasper, Hanna will work alongside Claudionor Coelho, vice president of engineering, and Rajeev Ranjan, chief technology officer, to further advance the company's breakthrough formal verification technology. These widely-respected technologists will lead a shared engineering team that will rotate between research and productization phases to deliver a pipeline of formal verification advances that are productized quickly and made available in production form to Jasper's customers.

"While at Intel, Ziyad was instrumental in the development of several generations of advanced formal equivalence and property verification systems, successfully deployed for achieving functional correctness in the design and implementation of nearly every Intel microprocessor design since the early nineties," stated Kathryn Kranen, president and CEO at Jasper Design Automation. "Ziyad brings to Jasper a wealth of microprocessor design and validation knowledge, as well as formal verification experience, which is why I am pleased to have him join the outstanding team that has helped to make Jasper the leader in deploying commercial formal verification solutions."

"It is not easy to leave behind the valued team of people with whom I have worked for many years, and come to know personally," said Hanna. "However, upon meeting Kathryn and the rest of the Jasper team, I found myself truly impressed with their passion and commitment to tackling even the most daunting customer design and verification challenges. I look forward to working closely with this team to meet our customer's growing design and verification needs by delivering even greater productivity and value with the JasperGold product family."

Hanna will be relocating from Israel to the United States to work at the Jasper headquarters office in Mountain View, California. He received both his B.Sc. and M.S. degrees in computer science at Tel-Aviv University, and is working towards his Ph.D. with research in "Abstract Modeling and Formal Verification of Microprocessors" at the Computing Laboratory of Oxford University.

About Jasper Design Automation

Jasper Design Automation, a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers, is the leader in successful deployment of formal solutions in production verification environments. The company's flagship product, JasperGold Verification System, is the first verification product to deliver complete "deep formal" systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all use modes, without any testbench development. JasperGold Express, Jasper's formal ABV solution, provides the industry's leading "light formal" solution, complementing simulation-based approaches by accelerating bug hunting as well as coverage attainment. The JasperGold family quickly isolates bugs with a fast, static debugging capability, and then proves the absence of bugs, trimming design schedules. For further details on how to ensure guaranteed correctness where it matters most, please visit www.jasper-da.com

Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan, InFormal, Proof Accelerators, Lossless Abstractions, Formal Scoreboard, and Design Tunneling are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.


For Jasper Design Automation
Francine Bacchini, +1-408-839-8153
Email Contact



Review Article Be the first to review this article

ClioSoft at DAC

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
ClioSoft at DAC
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise