|Partition-based incremental synthesis takes traditional block-based iterations one step further by localizing design changes within a partition.|
We are the only ones in the industry that has graphical representation, cross probing and an easy way to analyze the resources utilization and quickly remap to solve timing or other mapping problems.
We have given the tool to our partners. They have checked it themselves. Altera has checked it with its own design suite. In this case there are over 70 designs. They found significant improvements in quality of results for new products. Obviously, we do not know what those designs are. They have observed the same results we have. Xilinx has given us a quote saying “you know guys the capability you have been developing is needed because that this what our customers have been saying to us. That means you did a good job in the right places.” Pierre-Xavier of IP Extreme is an example of an end user that always faces challenges of maximizing the speed of their cores. They are creating IP. They want to make sure that their IP runs on the fastest clock possible. They realized in that case 17% improvement in Fmax which is very significant.
Where does the new Precision RTL Plus product fit into the Precision family?
Up to now we have had Precision RTL and Precision Physical. The new product lies in between. We believe that it will become our flagship product because of its unique capabilities. It has all the Precision RTL capabilities and features plus the first to market capabilities. Precision Physical is a superset. It also has the new features.
What is the pricing for Precision RTL Plus?
The starting price is $27,500.
Is that a time based license?
It is a node locked perpetual license.
How does that price compare with other member of the Precision Family?
Precision RTL starts at around $20K. Precision Physical is much more expensive. Precision Physical has capabilities for advanced physical synthesis, debugging and placement resuse/eco. Most of the time Mentor customers are not paying list price but are paying based upon what they buy overall.
If I completed a design using a Xilinx FPGA and Xilinx tools and wished to migrate that design to Altera and obviously not having used Precision RTL Plus for the original design, would I be able to do this as smoothly as if I had used Mentor’s product in the beginning?
If you started the design with our tools, that is the best way. It gives you the smoothest transition. What you are describing is very possible and is indeed being done. Many times people who are using other tools are coming to us for business and performance reasons. The transition of the design that was done with another tool to our tool is not painful.
Is it conceivable that if I used Xilinx tools or Alter tools for a design that I might end up with some IP from those vendors. If so, would that make it more difficult to migrate to the other vendor?
Yes of course. When you are using tools like Precision, it will enable you and even encourage you so to speak to minimize the use of IP that locks you into specific silicon. If you are using a tool from a vendor, you might end up using much more of those IPs. We support the IP flow of the vendors but obviously if you are using IP that is for a specific vendor, it will be more difficult afterwards to shift to another vendor. By using vendor independent tools we make sure it is the easiest for you to do. But of course IP is one of the methods to lock the customer to a specific vendor.
Do Zuken or Altium have anything in the FGPA synthesis arena?
If one wants to use FPGA prototyping for a large ASIC, one may need to partition the ASIC design to fit onto multiple FPGAs. How does this situation fit into the Precision RTL Plus flow?
There is a stage called partitioning whereby as you said correctly some big ASICs if you want to prototype all of them you need to partition it because it doesn’t fit into one FPGA. In this case you can either do it manually but when you have to partition into too many, you might want to consider automatic partitioning. For that approach we have a certified flow with a company called Auspy. For customers who need automatic partitioning because the ASIC is too big to fit into one FPGA, they can do manually and then use Precision or use the certified flow between Auspy and Precision.
Is this a different type of partitioning than the one you discussed earlier?
Yes. Before I was referring to cases where you have one FPGA and in order to benefit from incremental design flow, you need to partition the single FPGA design into multiple blocks. But it is still one FPGA. The second type is where you have a very large FPGA which can not fit into one FPGA. Therefore you have to partition the ASIC deign into multiple FPGAs.
Does Cadence, Synopsys or Magma have any offerings in FPGA physical synthesis?
Cadence and Synopsys are not in the physical synthesis market. Synopsys used to be but they are no longer. For Magma it is not their focus. They might have something. We don’t come across them.
When it comes to FPGA synthesis, you have four major players. You have Xilinx and Altera. We are cooperating with them but they have their own synthesis but only for their tools. You have of course Synplicity and Mentor. These are the four major ones. If you ask how Lattice or QuickLogic and other FPGA vendors do synthesis? The answer is that they usually oem synthesis software from us or from Synplicity. As far as we know, we are the leader in oeming software to FPGA vendors.
On the backend if you do not want to use your own board we offer off the shelf solutions. We are partnering with companies like ProDesign. The ecosystem to completely support FPGA and AASIC prototyping is there.
The top articles over the last two weeks as determined by the number of readers were:
When is the best time to look for a NEW OPPORTUNITY? Career advise article by article by Mark Gilbert, President EDA-Careers.
Mentor Graphics Reports Third Quarter Results Below Guidance; Reaffirms FY2008 and FY2009 Guidance Mentor Graphics announced that third quarter fiscal 2008 results will be below guidance issued on August 23, 2007. Revenue is expected to be approximately $185 million versus guidance of $200 million and non-GAAP earnings are expected to be slightly below break-even as compared to a previously estimated $.10 per share. On a GAAP basis, the company also expects a loss. Walden C. Rhines, chairman and CEO of Mentor Graphics, said “Revenue was short of guidance because unique circumstances on several large bookings caused revenue to lag bookings by a quarter. Because we see this revenue deferred by only a quarter, Mentor reaffirms its fiscal 2008 and 2009 outlook."
Cadence Announces New RF Technology to Ease Design of Nanometer Wireless Chips Cadence introduced Virtuoso® Passive Component Designer, a complete flow for the design, analysis and modeling of inductors, transformers and transmission lines. The new technology puts passive component design into the hands of analog and RF designers developing fast and complex wireless SoCs and RFICs. Starting from design specifications such as inductance, quality factor and frequency, the Virtuoso Passive Component Designer helps designers automatically generate the optimum inductive device for their specific application and process technology, resulting in higher performance and smaller area. A built-in accurate 3D full wave solver verifies the generated devices, eliminating the need for a dedicated inductor characterization run and reducing the design turnaround time.