Brown Bag Lunch: Sanguinetti & Sandler

* Mentor Graphics announced that Elektrobit Corp. used Mentor’s Catapult C Synthesis tool in designing its next-generation wireless products. Per the Press Release: “EB selected the Catapult C Synthesis product based on the tool’s ability to synthesize pure ANSI C++ and increase hardware designer productivity up to 10x.”

Ari Hulkkonen, Director, Wireless Systems at Elektrobit, is quoted: “Catapult delivers a level of productivity that we are unable to achieve using hand-coded RTL methodologies. The productivity benefits come from automatic RTL creation that eases design exploration, plus verification efficiencies delivered by the C testbench Catapult’s error-free RTL code.”

* Mentor Graphics also announced a collaboration with LeCroy to deliver a complete platform for USB-based protocol applications. Michael Romm, LeCroy’s Director of Product Development, is quoted: “Mentor’s Veloce family of advanced hardware-assisted verification solutions complements our USB test systems. One of our key customers, a world leader in consumer electronic and multimedia systems, can now perform rigorous testing of their latest applications on this integrated, high-performance verification platform.”

* MIPS Technologies announced that AMIMON has licensed the low-power MIPS32 M4K core for development of wireless HD audio and video transfer applications.

“To achieve the wire-like quality and speed of AMIMON’s wireless HD technology for consumer electronic devices, the underlying technology must offer the best possible mix of high performance, low cost and low power,” said Yoav Nissan-Cohen, CEO, AMIMON. “The MIPS32 M4K core delivers on this promise, and because it is small and synthesizable, it also offers the design flexibility we need to quickly get our products to market.”

* OCP-IP announced that Synopsys has joined the OCP-IP Governing Steering Committee. Other committee members include Nokia, Texas Instruments, Toshiba, and Sonics. Per the Press Release: “Synopsys is already active in OCP-IP’s working groups, and their DesignWare Verification IP for the OCP interface is a part of the CoreCreator verification toolset that all OCP-IP members receive.”

* Ponte Solutions announced a new interface between its YA System and the Laker layout tools from Silicon Canvas, which the companies say “lets design teams easily perform Critical Area Analysis (CAA) and repair, utilizing the full capabilities of Silicon Canvas's Laker.” Ponte VP of Markting and Business Developerment, Michael Buehler-Garcia, is quoted: "DFM issues must be tackled early to increase the likelihood of first silicon success, and that means doing DFM analysis at the IP level. [This] announcement, giving designers predictable, actionable CAA analysis within a premier tool like Laker makes IP-level DFM a reality."

* Ponte Solutions also announced an interface between its YA System and the Cadence Virtuoso platform that the companies say “allows IP designers to address CAA in an actionable manner during the creation of IP elements, standard cells, and memories. As CAA is both statistical and contextual in nature it has been difficult for designers to take specific measurable actions to reduce CAA issues … Ponte’s YA System addresses this problem by presenting the designer with prioritized CAA hot spots, which will ensure the most critical CAA effects as predicted by certified defect kits provided by the leading foundries, are identified and corrected.”

Chartered‘s Walter Ng is quoted: “It is important that designs at 65nm and below consider the impact of DFM during development. This is a good example of a real design solution resulting from companies teaming up to develop the appropriate interfaces which allow designers to fully utilize the capabilities of today’s advanced nanometer process technologies.”

* Ponte Solutions and Blaze DFM announced delivery of the first modeling elements committed to Si2’s DFM Coalition last year. These contributions are the primary drivers for the critical area analysis and lithography elements of Si2’s DFMC efforts. The companies say that Ponte’s model-based yield analysis technology allows yield sensitivity analysis for identifying critical areas, and will be made available royalty-free to Si2 and DFMC members for standardization purposes, including modification and benchmarking for the next three years.

* Sagantec announced its work with TSMC resulted in the development of Sagantec’s DFM-Fix. Per the Press Release: “DFM-Fix speeds turnaround time by automatically addressing hotspots in all critical layers at all design levels, including key building blocks such as library, memory, IP and custom blocks. It also provides automated handling of post-implementation hotspots caused by boundary proximities and inter-level effects … TSMC and Sagantec tested DFM-Fix on multiple complete designs with hotspots in various layers. In all test cases, DFM-Fix automatically corrected most of the hotspots, with correction rates of 95% and above in most cases. The flow also proved highly time-efficient, running all test cases in under three hours on a standard quad-CPU platform.”

Coby Zelnik, Sagantec’s EVP of Marketing, is quoted: “Most lithography-related hotspots are found at the front-end and low metal critical layers in the IP infrastructure and macros of SoCs, as well as in memory and custom designs. These hotspots cannot be fixed by routing-level solutions. DFM-Fix addresses these hotspots very effectively for our mutual customers.”

* SAME 2007 Forum, which took place in early October in Southern France, announced 950 visitors, 46 exhibitors, and 23 sponsors. Awards at the conference including Best Paper, Best Start-up, and Best Poster and can be seen on the website at

* Sarnoff Corp. and Carbon Design Systems announced that Sarnoff has licensed Carbon's model generation technology to develop cycle-accurate system models directly from its RTL source code. Sarnoff’s Michael Piacentino, is quoted: "We selected Carbon Model Studio as a key component in our move to virtual platforms for early software development. Carbon allows us to create system models directly from our RTL, so we don't have the burden of maintaining two separate modeling development efforts."

* Si2 [Silicon Integration Initiative] announced that Synopsys has donated an oaTcl-based OpenAccess graphical visualization program (oaViewer) to the OpenAccess Coalition. OaViewer enables software developers of OpenAccess API-based programs to easily view design data such as hierarchical schematics and layouts including PCells. Synopsys VP Rich Goldman is quoted: "This is an important step towards analog design tool interoperability. We see this donation and the recent work in Interoperable PCell Libraries [IPL] to be significant improvements in making OpenAccess a truly open custom analog environment. We hope to inspire more donations to enable OpenAccess to become a complete usable analog solution."

* Stream Processors Inc. [SPI] says it chose Sequence Design's PowerTheater for power management and low-power architecture evaluation for their new processor design, and hence reduced power 20 to 50 percent. "Based on SPI's revolutionary Stream Processor architecture, our current Storm-1 family delivers the industry's lowest Watt per GOPS (Giga Operations Per Second), and PowerTheater has enabled us to further reduce power by slashing analysis iteration cycle times by 3-4X while the sophisticated tools suite provided comprehensive feedback," is the quoted from Paul Filanowski, SPI's Vice President of Hardware Engineering, in the Press Release.

* SynaptiCAD announced it has acquired exclusive development and distribution rights to V2V, HDL translation software from Alternative System Concept (ASC) for HDL translation for an undisclosed amount. V2V is a set of command line tools that perform automatic translations of source code from VHDL to Verilog and vice versa.

Dan Notestein, President of SynaptiCAD, explains the reason for the technology transfer: "A lot of our customers have expressed interest in translating IP and legacy models so that they can debug in a single-language environment. After investigating the available options, we determined that ASC had the best technology for doing these conversions."

* Synopsys aannounced it has extended low power management capabilities in the Synopsys Galaxy test solution “to significantly reduce the time and effort needed to generate high-quality, power-aware manufacturing tests for ICs. The TetraMAX ATPG solution now creates tests reflecting designers' power budgets, and the DFT MAX scan compression product further automates integration of DFT structures in designs that deploy advanced low power management techniques.”

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