You can reduce power consumption by more than half without any area penalty at 65 nm!
Typically, the silicon area of a 6-Mbit instance ROM in 65 nm will decrease as far as 0.63 mm2 with only 1.2 uA leakage current, thanks to the key "two-in-one" patent.
For a RAM instance of 64 kbits, the power consumption is a mere 9 uA/Mhz and leakage in power-down mode is 0.91 uA.
More information on http://www.dolphin.fr/flip/ragtime/65/ragtime_65_ram.html
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