Dolphin Integration announces its ultra low power, low leakage and High density 65 nm ROMs and RAMs

You can reduce power consumption by more than half without any area penalty at 65 nm!

France, October 11, 2007 - DOLPHIN Integration marks their presence at 65 nm, with the patented tROMet Phoenix, optimized for ultra high density and very low leakage, as well as the spRAM Uranus optimized for Low power and Low leakage.

Typically, the silicon area of a 6-Mbit instance ROM in 65 nm will decrease as far as 0.63 mm2 with only 1.2 uA leakage current, thanks to the key "two-in-one" patent.

For a RAM instance of 64 kbits, the power consumption is a mere 9 uA/Mhz and leakage in power-down mode is 0.91 uA.

More information on http://www.dolphin.fr/flip/ragtime/65/ragtime_65_ram.html

About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in Microelectronics to "Enable mixed signal Systems-on-Chip", with a quality management enabling reactivity for innovation.




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