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* In related news, Pyxis Technology announced it is delivering software products based on a multi-year license agreement with PDF Solutions. The companies say they’ve been working together since early 2006 to “leverage the pDfx technology to address manufacturing complexities of routing in advanced technology nodes. The incorporation of pDfx into NexusRoute is designed to deliver faster design closure and yield ramp to clients and better predicted yield for designers by bringing real world manufacturing data directly into the integrated circuit (IC) implementation phase. “

* Silicon & Software Systems Ltd. announced that NXP used “a full suite of IC, software and hardware design capabilities” from S3 in developing NXP’s newest STB100 SoC-based platform for consumer set top box (STB) applications. NXP VP & GM, Guus Frericks, is quoted in the Press Release: “With the STB100 we are enabling rapid development of entry-level STBs by providing complete hardware and software turnkey solutions for global digital satellite, cable and terrestrial markets while also reducing achievable price points. Once again S3 has proven that their technical expertise, experienced resources and right-first-time delivery proved to be hugely valuable to NXP in bringing our solution to market on time and within budget.”

* S3 Graphics, a subsidiary of Via Technologies, says it’s using Sequence Design's Cool Products “for accelerated design closure, achieving 1GHz performance in a single pass, when implementing their next-generation 3D graphics chips … The next generation chip [includes] over 10M instances, multiple clocks ranging from 800MHz to1GHz, 90-nanometer Fujitsu high performance libraries, and mixed Vt.”

S3 Engineering Manager Xin Chang is quoted: "S3 saved several months on achieving design closure based on CoolPower's ability to concurrently solve for, analyze, and optimize timing and noise. We use Sequence for final signoff with an Astro flow, and Cool Products deliver faster run time, accurate results, and reduced iterations between different tools."

* Simucad announced version 1.3 of the company’s VBIC bipolar junction transistor model, which contains “all important modeling and implementation enhancements required for modern bipolar technology and circuit design … New features advance the modeling of modern SiGe HBTs by introducing a description of quasi-neutral base recombination and band-gap grading effects … The electro-thermal modeling is enriched with temperature-dependent Early voltages and a nonlinear temperature-dependent thermal resistance for self-heating critical applications.”

* SMSC and Harman/Becker Automotive Systems announced the companies are “committed to open and license, on a royalty-bearing basis, their proprietary Data Link Layer IP for existing and future generations of the Media Oriented Systems Transport (MOST) multimedia network. By making available their key technologies for the lower layers of MOST, semiconductor companies will be provided an opportunity to manufacture and supply chips that incorporate an interoperable MOST interface.”

* Stratosphere Solutions and Cadence Design Systems announced a collaboration the companies say will increase yield at 45-nanometers through “improved process modeling, analysis and implementation flows that allow foundries, IDM’s, ASIC and COT designers to increase the quality of their results … The collaboration uses the new STTA features in Cadence Encounter [to achieve yield improvements].”

Stratosphere Co-founder and CSO, Prashant Maniar, is quoted: “The Cadence-Stratosphere collaboration empowers our mutual customers to significantly mitigate impact of process variation, improve performance predictability, and prevent silicon failures. Such collaboration across the value chain is critical to meeting the demands of cutting-edge electronic design for the foreseeable future.”

* Synopsys and Oki Network LSI announced that OKI achieved “15 first-pass verification successes of complex SoCs within the first year of adopting SystemVerilog and Synopsys' Discovery Verification Platform.”

Takahiro Kobori, Senior GM for the Design Business Group at OKI, is quoted: "After a careful evaluation of available solutions, we adopted Synopsys' proven SystemVerilog solution, including VCS, VCS Verification Library and the VMM, to deploy our next-generation verification services. Customer demand for our new VMM-based service has been very strong from the beginning, and today our new customers are choosing SystemVerilog and the VMM for their projects."

* Synopsys, as a member of the ARM Connected Community, announced “significant performance improvements” in the newest version of Synopsys’ HSPICE simulator has “enabled ARM to accelerate delivery of highly optimized memory and standard cell building blocks for SoCs.” Sounds like a win-win situation.

* Synopsys also made a joint announcement with Signal Integrity Software, Inc. to declare the integration of SiSoft's Quantum-SI tool and Synopsys' HSPICE that the companies say will “deliver robust timing and signal integrity analysis for package and PCB design.”

SiSoft VP Todd Westerhoff is quoted in the Press Release: "Quantum-SI extends HSPICE to provide a comprehensive design and analysis environment for pre- and post-route analysis that allows customers to seamlessly mix IBIS and transistor-level models. Our customers have benefited greatly from HSPICE's accuracy and scalability for detailed signal integrity and power modeling applications."

* Synopsys also announced that the Dubai Silicon Oasis Authority has chosen Synopsys' Professional Services and Synopsys' Pilot Design Environment to establish the Dubai Circuit Design (DCD) center. The organizations say this “center is the region's first chip design center for physical implementation of advanced ICs.” They also say that “Synopsys supported DCD with guidance in hiring staff and by providing management and technical expertise. With the help of Synopsys, the DCD office is now operational and engineers are fully trained on the latest Synopsys tools and technologies. DCD customers are creating multi-million gate, multi-voltage designs in 90-nanometer and below process technologies … DCD aims to become the leading regional force in chip design innovation using state-of-the-art Synopsys tools, flows, and methodologies to implement complex silicon designs.”

* Synopsys wasn’t done, however, because they also announced that Global Unichip Corp. is using Synopsys' TetraMAX ATPG technology. GUC’s Louis Lin is pleased: "As our design complexity increased and our manufacturing process shifted to 90- and 65-nanometers, delay testing became mandatory to enhance test coverage. By adopting the TetraMAX at-speed test solution, we improved test quality for several projects. In addition, we used DFT MAX scan compression to reduce test data volume by more than 90 percent on several designs, and the compressed patterns were later successfully applied on our testers to verify working silicon.”

* Synplicity announced an addition to its HAPS (High-performance ASIC Prototyping System) product family, the HAPS-51, which the company says “leverages the Xilinx Virtex-5 LX330 and on-board memory to deliver faster ASIC verification. Previous HAPS systems employed daughter boards for memory access, while the new HAPS-51 uses memory located on the board and next to the FPGA device. As a result, the HAPS-51 system provides a cost-effective, high-performance prototyping solution that reduces development time for today’s challenging SoC designs.”

Lars-Eric Lundgren, GM of Synplicity’s Hardware Platforms Group, is quoted: “The unique features in the HAPS-51 system, combined with Synplicity’s FPGA synthesis and debug software, equips design teams with an outstanding solution for verifying the functionality of today’s most advanced and challenging designs.”

* TEA Systems announced enhancements to its Vector Raptor overlay and double patterning lithography control: “The results from a calculation of the systematic variations in overlay modeled data can be used as a feedback mechanism to scanner positioning or as a highly accurate method of estimation of positioning errors in locations on the field, wafer or lot not actually measured; full-wafer overlay simulation employs the systematic errors of the process to estimate distributions; and lot correction optimization for examining the effects of various methods of correction averaging.”

* Virtutech announced an API that will incorporate processor models from IBM's Mambo simulator into Virtutech's Simics full-system simulator. Virtutech would like to remind the reader that the company previously announced “IBM is leveraging Simics for its POWER Server product line. [Now], with this new interface, IBM can deploy Simics faster …By incorporating its Mambo processor model into Simics, IBM enables its developers to leverage the Simics virtualized software development platform to identify design issues that may affect functionality and performance far earlier in the development cycle, when they are much less costly to correct.”

Virtutech CEO John Lambert is quoted in the Press Release: "Our customers request more processor models with earlier availability for deeper and broader deployment of Simics. Our interface with the IBM golden processor model from Mambo is a perfect path to support this growing market requirement. Furthermore, this announcement is another milestone in the IBM and Virtutech relationship in support of IBM's POWER server product line development."

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