Cappuccino & Creativity: Sangiovanni-Vincentelli, Sentovich, and Szymanski
Ed also noted: “A lot of our customers are using Sandwork, as are lots of Cadence and Mentor customers. Even though we’re acquiring Sandwork, it’s our goal to maintain the products to that same level of opening in supporting those simulators.” It will be interesting to touch back with Ed in a year so and find out if Synopsys has succeeded there.
4 – News that’s noteworthy
* Agilent Technologies announced a donation of software, support, and training valued at $13 million to a new hub of the Georgia Electronic Design Center (GEDC) in Atlanta, a location sponsored by Georgia Tech. The organizations say, “The new Agilent EDA Simulation Center will facilitate RF and microwave-system and circuit-design instruction and research for students, and serve as a catalyst for start-up companies involved in wireless communications design This agreement is part of the newly created Agilent EEsof EDA University Alliance program”
Joy Laskar, Director of GEDC, is quoted in the Press Release: "Agilent's EDA tools help us continue to advance wireless technology and support our students, as well as to encourage and support start-up companies. We also want to contribute to the success of other academic and non-profit institutions through sharing our experience in this partnership. We are making plans to release large portions of work using the Agilent EEsof EDA platforms for academic use."
* Altera Corp. announced its Quartus II software version 7.2. Chris Balough, Director of Software and Embedded Marketing at Altera, is quoted: "With our latest Quartus II software, our productivity advantage has improved from 2X to 3X compared to our competitor's solutions, enabling our customers to compile their designs faster and meet their aggressive time-to-market goals."
* Altos Design Automation and Cadence Design Systems announced the companies “have qualified 45-nanometer and 65-nanometer statistical static timing analysis (SSTA) models generated by Altos Variety in S-ECSM format for use with the new statistical timing analysis technology in the Cadence Encounter Timing System and SoC Encounter RTL to GDSII system The test structures used to qualify the flow came from a number of different customers using different foundries.”
* ARC International released its VTOC 4.0 toolset, which was designed “for creating 100 percent cycle accurate C++ and SystemC models from Verilog and VHDL RTL.” The new release includes “a code analysis system that enables developers to generate C++ and SystemC models that are more efficient and achieve higher performance.”
* ARM announced the ARM Cortex-A9 MPCore multi-core processor and ARM Cortex-A9 single core processor, which the company says are “compatible with other Cortex family processors and the popular ARM MPCore technology [and] deliver highly scalable and power-efficient solutions by leveraging a dynamic length, 8-stage superscalar, multi-issue pipeline with speculative out-of-order execution capable of executing up to four instructions per cycle in devices clocked at 1+Ghz.”
* ARM also announced a collaboration with 6 companies, which the organizations say will result in “the development of a Linux-based open source platform for next-generation mobile applications.” The 6 companies include: Marvell, MontaVista, Movial, Mozilla, Samsung, and Texas Instruments. Instat’s Jim McGregor is quoted in the Press Release: “A critical component of success in [the ultra-mobile devices] market will be building on industry standards that promote innovation in silicon, systems, and most importantly, software solutions. Through open standards and growing industry support, Linux naturally promotes such innovation.”
* Finally, ARM announced the RealView Profiler tool designed to “enable non-intrusive analysis of software performance and code coverage of real system workloads running over minutes, hours, or days [The tool] includes comprehensive analysis of both statement and branch code coverage, enabling software testing to achieve and demonstrate 100% code coverage to ensure the highest level of software validation The RealView Profiler is a plug-in to the Eclipse IDE.”
* Berkeley Design Technology announced that picoChip's PC102 multicore signal processing device “has a 40-fold advantage in price-performance over traditional DSP processors solutions in key communications benchmarks, and 8-times higher absolute performance. The BDTI Communications Benchmark (OFDM) results demonstrate that the PC102 picoArray can implement 14 benchmark channels in a single device running 160MHz The PC102 is the first volume-shipping multi-core product to be submitted to independent audits for performance.
* Cadence Design Systems announced that Renesas Technology Corp. is using SSTA technology Cadence’s Encounter design platform as part of its “next-generation” design flow.
* Carbon Design Systems announced its Carbon Model Studio, which the company describes as “a solution for the automatic generation, validation and implementation of hardware-accurate software models, enabling a design team to begin software development and debug before silicon System architects can use Carbon Model Studio for architectural analysis and profiling. Software engineers can develop and debug embedded software, firmware, drivers and diagnostics concurrent with hardware development. Additionally, Carbon Models can be securely distributed to third-party partners to accelerate adoption of an IP provider's technology devices.”
Carbon CTO Bill Neifert is quoted in the Press Release: "Accurate models are the foundation upon which any successful virtual platform is built. Model Studio is enabling our customers to deliver first-pass system success by quickly generating models that can plug into the virtual platform environment of their choice."
* Chip Estimate and the FSA announced a collaboration which the organizations promise will “bring greater value to the semiconductor design community with FSA's IPecosystem Tool Suite. With this agreement, vendors now have an option to upload their Hard IP Quality Risk Assessment Tool risk profiles’ to Chip Estimate's chip planning portal. In addition, Chip Estimate users have the option to request a vendor's risk profiles or request that a vendor complete the Tool for their IP or family of IP within their portfolio. These features have been released as part of FSA's Hard IP Quality Risk Assessment Tool version 3.0.”
* Cimetrix released its EDAConnect Interface A software “solution,” which the company describes as “a client-side software library designed to assist IDMs and third-party software providers in creating applications that can utilize the rich data available via the new Interface A connectivity standards commonly known as Equipment Data Acquisition (EDA) Created by Semiconductor Equipment and Materials International (SEMI) in cooperation with International SEMATECH Manufacturing Initiative (ISMI), the Interface A standards provide a second connectivity port for on-demand, high-quality data to be used by IDM critical equipment engineering systems such as Advanced Process Control.”
* Cimmetry Systems, a subsidiary of Agile Software, which was recently acquired by Oracle, announced its AutoVue v.19.2, which the company says “solidifies Cimmetry’s presence in the electronics and high-tech market with new EDA centric product offerings to address the specific requirements of PCB design and contract manufacturing.”
* EVE announced a partnership with ARM to integrate the tools of the two companies “to produce a high-end co-emulation environment.” Per the Press Release, “The ARM RealView SoC Designer ESL design software will be coupled and integrated with EVE's ZeBu hardware-assisted verification platform for early architectural exploration and prototyping Designs can be progressively moved from simulation into emulation by removing models from the SoC Designer tool and synthesizing the RTL on ZeBu.”
Lauro Rizzatti, is quoted in the Press Release: "The co-emulation platform offered through the integration of the SoC Designer tool and ZeBu is an effective means of deploying system level models of ARM and third party IP."
* Elliptic Semiconductor and Impinj announced an agreement to “collaboratively develop a secure, standards-based SoC reference architecture for content protection applications such as digital rights management and conditional access. The reference architecture integrates Elliptic’s embedded security module and Impinj’s AEON multi-time programmable nonvolatile memory core to counteract embedded system threats such as reverse chip engineering and cryptographic algorithm security breaches [The companies hope to] utilize security technologies that have been validated through extensive testing with real-world applications by the National Institute of Science and Technology, ANSI and the NSA; leverage logic based NVM for storage of embedded, on-chip secrets and root-of- trust; and define a security boundary within the SoC that ensures that only fully validated software processes and local hardware resources can access secret keying material.”
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