Mindspeed Uses Databahn DDR Controller IP in its High-Performance Comcerto 100 Series SoCs
"We succeeded with a very aggressive design schedule for the Comcerto 100 processor," said Surinder Dhaliwal, executive director of Core Technology at Mindspeed. "There were significant technical challenges and time-to-market pressures involved, but Denali's flexible DDR controller IP provided an optimal solution for the DDR DRAM subsystem, and allowed us to meet the design requirements of the design. Denali's industry-proven reputation for high-quality IP and memory expertise played a key role in this success."
The Databahn product provides a comprehensive infrastructure for configuring, analyzing, and generating the optimal memory controller for any given application. Denali's Databahn DDR memory controllers offer a powerful, multi-port solution with configurable features and functionality to satisfy system performance requirements.
Mindspeed's Comcerto 100 Series SoCs provide a range of pin-compatible devices that allow customer premise equipment (CPE) manufacturers to design a family of advanced gateway solutions using the same software architecture to support broadband home routers, enterprise service routers, and high-end integrated access devices. The Comcerto 100 Series device architecture includes a pair of high-performance ARM 11 processors, a security engine, a 64KB on chip memory, a 128KB L2 cache, plus a 64-bit wide, 165MHz multi-layer interconnect bus and built-in QoS and traffic management capabilities. These new devices enable service providers to deploy sophisticated, reliable services with the high-packet throughput required for delivering next-generation multimedia content to wireless home entertainment networks.
"High-quality IP is key to solving DDR memory system requirements, especially when dealing with sophisticated and high-throughput applications," said Brian Gardner, vice president of IP products for Denali. "With Databahn DDR controllers, we are providing customers with reliable and flexible memory systems that integrate well into the system environment. We also realize the importance to provide a solid roadmap of IP that enables customers to track DDR device economics for an overall IP solution that includes BOM considerations, and we are pleased to be working with Mindspeed to achieve this."
About Databahn DDR Memory Solutions
Denali's Databahn DDR memory solutions ensure compatibility with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, GDDR3, and LP-DDR devices from all major memory vendors and currently supports 27 vendor process nodes. Deliverables include: RTL and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. Databahn controllers are compliant with all the latest memory devices.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Denali and Denali Software are registered trademarks of Denali Software, Inc. Databahn is a trademark of Denali Software, Inc. All other trademarks are of their respective owners.
Editorial contact: Pierre Golde Denali Software, Inc. (650) 461-7262 Email Contact
Web site: http://www.denali.com/