"With this collaboration, wireless chip designers now have a comprehensive set of interoperable design tools, methodologies and process technologies necessary to achieve shorter, more predictable design cycles for highly integrated, 65-nanometer RF and AMS designs," said Kuo Wu, deputy director of Design Service Marketing at TSMC. "The combination of TSMC process technology and libraries and Cadence design flow provides a full, end-to-end solution for designers of wireless SoCs."
The new TSMC 65-nanometer RF PDK and Cadence RF and analog design flow support the Cadence Virtuoso IC design platform. Representative blocks from the Cadence AMS Methodology Kit and Cadence RF Design Methodology Kit have been validated through the Cadence RF/AMS simulation environment, and are compatible with TSMC's PDK in 65-nanometer technology. The RF and AMS design-flow demonstration packages are a part of the continuous collaboration between the two companies, to build and enhance comprehensive design infrastructures. Together, Cadence and TSMC focus on enabling support for designers of advanced SoCs, such as wireless and networking devices, which use analog, mixed-signal and RF technology in addition to digital content.
The demonstration packages contain TSMC 65-nanometer RF-enabled design examples for RF and AMS block creation, application notes and methodology documentation, and a design example-circuit database with complete execution scripts and flow, covering simulation, design creation and analysis, allowing designers to observe the complete flow in an actual design. The new Virtuoso IC based 65-nanometer RF PDK and TSMC's Nexsys 65-nanometer LP standard cell library are both downloadable from the TSMC Web site.
"Both Cadence and TSMC recognize that collaboration on projects such as the 65-nanometer wireless design-flow demonstration package result in more holistic solutions that benefit the design community. In this effort, we're enabling designers in the wireless segment to improve the quality and predictability of advanced SoC designs," said George Kuo, group director of industry alliances at Cadence. "We are looking forward to continuing this technology collaboration and strengthening methodologies for application-specific design."
Designers can access the demonstration package from Cadence Web site starting July 1st, 2007.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven libraries, IP and design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65-nanometer production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com
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For more information, please contact:
Cadence Design Systems, Inc.
TSMC North America