Timing and Signal Integrity – CLK Design Automation

When you announce on the 21st, will you identify the IDM?
I doubt it knowing the way things usually work.

The top articles over the last two weeks as determined by the number of readers were:

HP Reports Second Quarter 2007 Results HP announced financial results for its second fiscal quarter ended April 30, 2007, with net revenue of $25.5 billion, representing growth of 13% year-over-year, or 10% when adjusted for the effects of currency.   GAAP operating profit was $2.1 billion. As outlook HP estimates Q3 FY07 revenue will be approximately $23.7 billion to $23.9 billion.

Mentor Graphics Expands Questa Functional Verification Platform and Targets Low-power Designs Mentor announced it has expanded the comprehensive Questa verification solution which includes the new Questa 6.3 functional verification platform addressing low-power verification, and powerful verification management capabilities that enable closed-loop management reporting, analysis and documentation. It also includes improved debugging and version 3.0 of the industry's first open-source standards-based Advanced Verification Methodology (AVM).
The Questa 6.3 verification platform will ship in Q2 2007 and includes access to the Advanced Verification Methodology portal. Configurations start at $24,000 USD for a 12-month license.

Cadence Introduces Industry's First Complete Custom IC Simulation and Verification Solution Cadence unveiled  Virtuoso Multi-Mode Simulation (release MMSIM 6.2), an end-to-end simulation and verification solution for custom IC that uses a common, fully integrated database of netlists and models to simulate analog, RF, memory, and mixed-signal designs and design blocks. This allows designers to switch from one simulation engine to another without compatibility issues or interpretation impacts, so consistency, accuracy, and design coverage are improved, while cycle time and risk are reduced. The overall result is lower cost of adoption, support, and ownership, and faster time to market.

Virtuoso Multi-Mode Simulation is tightly integrated with the new Virtuoso custom design environment, enabling a complete design-to-verification methodology.

Pro Design Launches Next Generation of CHIPit ASIC Prototyping Systems Pro Design, a leading supplier of high-speed ASIC and SoC verification platforms, today announced the launch of its CHIPit V5 series, the next generation of its successful CHIPit product family. The new generation of CHIPit High-Speed ASIC Prototyping Systems is very flexible, scalable and is available with 1 to 6 Xilinx Virtex-5 LX330 FPGAs. Depending on the configuration, the system handles ASIC design capacities up to 8 M ASIC gates

UMC Expands Support for Mentor Graphics' Calibre YieldAnalyzer to Deliver Production Proven DFM Flow Mentor announced that UMC has expanded its support for the Calibre nm Platform with Calibre YieldAnalyzer for all major design flows for its 90 (nm and 65nm processes. Mentor and UMC have worked collaboratively to introduce DFM capabilities that give designers highly valuable information to guide physical design improvements that can increase production yields.

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