DAC & DFM – Once More, with Feeling

Chenmin Hu – There are fundamental underlying problems that occur with every new technology adoption process. Where DFM is concerned, it’s fear of the unknown brought on by the reality that manufacturing-process variability has exceeded the tolerance of targeted design performance. New design challenges demand a paradigm shift in the design-to-manufacturing ecosystem in the relationship between design and manufacturing. In other words, the EDA vendors and fabless designers as well as the fabs all must exit their comfort zones to get a handle on DFM. For example, the fabs and IDMs foresee potential manufacturing problems with new advanced processes and are already raising red flags. In turn, the EDA vendors are trying to understand these manufacturing problems that have been fairly foreign to them until recently so that they can develop DFM tools to remedy the impending manufacturability and yield crisis. And tool users need to take steps to incorporate DFM tools in their new design flow.

Dave Holt – Because it is in everyone's interest to keep Moore's Law moving forward. And right now the economics of moving each step down the lithography curve imperil more and more designs as they won't have sufficient ROI. Thus, anything that can be done to improve the economics of nanometer-process nodes allows more business (design starts) to move to those processes.

Dave Reed – DFM has been on the radar screen for a long time, but it wasn't until recently that things such as leakage power became critical. At 130 nanometers, leakage power was negligible, but at 65 nanometers, leakage can account for more than 50 percent of a chip's total power consumption. When something goes from non-existent to acutely critical in such a short period of time, it gets people's attention.

Gary Smith – New problems, market inhibitors, new challenges, new opportunities to stay ahead of the fabless competition.

Joe Sawicki – The industry is excited about DFM because it directly affects TTM and manufacturing yield, the primary determinants of IC profitability. Foundries and designers working at 65 nanometers and beyond are realizing that designs at these geometries are much more sensitive to manufacturing process variations than in the past. Design rules can’t be specified as simple constraints any more. They’re now either complex multivariable equations or based on sophisticated simulations of the manufacturing process itself. What designers need are tools that give them insight into the impact of manufacturing variability on the yield of their designs. There’s a great opportunity to have a big, positive impact on manufacturing yield at nanometer-design nodes by making relatively simple, and ideally automated, modifications to the physical design. Effective DFM tools provide specific guidance to designers and offer a complete solution that covers the general checks found in a physical verification tool, as well as the specific checks found in model-based solutions.

John Lee – Yield is a struggle for the fabs at 65 nanometers. 45 nanometers won't be easier.

Kamal Aggarwal – It’s one of the areas where new challenges and opportunities for EDA lie, which explains interest from the EDA community. Some of the DFM challenges at today’s process nodes are blurring conventional boundaries and forcing enhanced information exchange amongst fabs, fabless companies, and EDA companies. That explains the additional interest from various players in this space.

Michael Buehler-Garcia – Two reasons. (1) Technical: The impact of process variability as we migrate to smaller nodes is impacting “core designer issues” like timing, speed, and power. When DFM is tied to these core issues, it impacts all designers versus “the DFM Team”, whomever they are! (2) Business: DFM requires all elements of the design ecosystem to work together, so developing a business model where everyone gains is the end game. DFM will drive us to this model ahead of everything else.

Mitch Heins – Foundries are bothered because they can regulate profit margin based on defect density and yield. IDMs are bothered because they want to maximize fab "useful capacity utilization" for $3 billion fab ROI. EDA start-ups are bothered because it's not focused on the RTL-2-GDSII business of the broadliners. EDA leaders are bothered because of potential for new business models (Cadence CEO Mike Fister, Q1-07 analyst session). The press is bothered because of "Dollars For Marketing" and potential for innovation and growth. The tools users are bothered because all of the above are bothering them. If I were a design manager, I'd just be worried about whether or not my chip was going to work. If you look at the physics of 45 nanometers and 32 nanometers, you have to have a lot of things work perfectly for your part to even work, let alone at speed, power, etc.

Prasad Subramanian – The resolution of the manufacturing equipment is unable to keep up with the shrinking geometries. As a result, patterns drawn in the mask are not necessarily the same as those that appear in silicon. This, along with the increase in process complexity, creates many more opportunities for manufacturing problems. DFM is the key to resolving these issues.
 
Prashant Maniar – Customers (fabs and designers) are struggling to migrate designs to smaller geometries to meet end-consumer requirements. Failure of successful migration has a significant economic downside to the industry. Fabs are trying to drive yields (defect limited, systematic, parametric) higher and designers are trying to make sure they get predictable performance and adequate yield for each part. This creates an opportunity for EDA vendors to sell new tools, and the press to write compelling stories for the industry

Rob Aitken – DFM is addressing a genuine issue: Without feedback from the manufacturing process, it’s difficult to draw the right balance between standard optimization criteria (power, performance, area) and yield/manufacturability. Each generation from 130 through 45 nanometers has needed additional information to be passed back and forth. The information exchange is happening, but tools make it easier and help it fit in the flow.

Srini Raghvendra – DFM addresses yield and time to market. Both of these issues directly affect our customers’ top and bottom lines, thus the intense interest.

Sudhakar Jilla – DFM is a new phenomenon caused by the current manufacturing limitations. Moore's law and manufacturing physics are not in sync. DFM calls for a new breed of tools to address the problem and hence the excitement.

Tom Wong – 1) Because you CANNOT make silicon yield if you do not have DFM solutions. It is all due to the lithography gap – we are using a 193-nanometer light source to print 90/65/45-nanometer silicon. 2) Because the VCs have invested a lot of money in DFM start-ups over the last 3 years. 3) Because Brion was acquired for over $250 million.

Yervant Zorian & Ken Potts – The challenges of next generation device physics are driving the increased need for DFM. This is readily apparent to all participants. The ecosystem will embrace DFM capabilities that take a system approach to the solution space, such as the Star Memory System.

*************************************

13) Will you attend any DFM sessions at DAC? If so, which ones?

Atul Sharan – Not sure about any others, but I will definitely attend the sessions where several of Clear Shape's DFM customers will present to designers about their DFM approaches in our own suites!

Chenmin Hu – Yes, the DAC Pavilion Panel: “DFM: Prevention or Cure”.

Dave Holt – We have technical folks who will be in attendance. I'll be working on the floor meeting with customers, partners, and the press.

Dave Reed – Not only are we attending, but we're hosting a number of sessions. Hands-on tutorial: "Standard Cell Library and Hard IP Design" presented by Blaze DFM, Ponte Solutions, and Sagantec (June 4, 9am - 12pm, Room 11A). Hands-on tutorial: "Manufacturing-Aware Optimization" presented by Blaze DFM and TSMC. (June 6, 2:00-5:00 PM, Room 11A). Our engineering staff will also be presenting the following technical papers and tutorials: "Modeling for DFM/DFY" (June 4, 12:00 - 5:00 PM, Room 6A); "Line End Shortening is not Always a Failure" (June 5, 4:30 - 6:30 PM, Room 6F); "How Design Meets Yield in the Fab" (Friday full-day tutorial, June 8, Room 6D).

Gary Smith – Probably not.

Joe Sawicki – Mentor is giving a whole host of presentations and demos at DAC. We’ll have presentations at the Mentor DFM kiosk in the Mentor booth, presentations in the Mentor booth suites, and demos and presentations in the Intel, Common Platform, and UMC booths. In addition, IBM will be describing how they use Mentor DFM tools within the Common Platform Alliance at the Mentor Network event at DAC. (Monday, June 4, 4:00 at the Mentor booth).

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