News Alert/SUPERLOG Creator Being Courted by EDA Leaders-SystemVerilog Gains Ground


July 18, 2002 - Los Altos, Calif. - EDAToolsCafe learned today from a reliable source that Co-Design Automation, Inc. was purchased by either Synopsys, Inc. or Cadence Design Systems, Inc., most likely the former.

"Synopsys finally realized SystemC is not working," noted the source. And apparently the founders of Co-Design had tried to raise additional money but did not achieve the results they were looking for. This sale looks like they decided to cash in, the source said.

"This means Superlog is dead. SystemVerilog has been gaining ground and Synopsys realizes that," the source added.

Dennis Brophy, chairman of standards body Accellera, all but confirmed the rumor by saying that he had also heard the highest bidder was Synopsys. Accellera is proposing SystemVerilog as the standard set of extensions to the Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models.

"This is a great thing for SystemVerilog and a good thing for the continuing work Accellera has been doing with the standard. Synopsys has recognized this," Brophy said. "We have taken some big steps in the past few months with end users and Co-Design has done quite a bit of work to elevate it to the next level and also couple it with the business imperative." (For instance, Intel said during DAC2002 that it would transition to System Verilog within a few years.)

In addition, Accellera has "received strong backing from a major technology component in design flows today - Design Compiler, which Synopsys said would be moving it in support of SystemVerilog," Brophy continued.

Brophy speculated that Co-Design recognizes the financial strength of Synopsys, and also realized they needed more capital to keep development going. "This is really Synopsys giving the Co-Design technology a permanent safety net so that the tech doesn't go away. They've taken the big "to do" off its list to strengthen future access to this technology."

Further, Brophy said he does not see Synopsys' System C language as the single language of the future, as many have predicted will emerge, however it will not go away for DSP-based design, and sees it continuing to be used in numerous tools, as designers continue to use DSPs in designs. "For anyone working with DSP solutions, this [System C] technology will continue to play an important role," Brophy added.

SystemVerilog is a set of extensions for a higher level of abstraction for modeling and verification with the Verilog Hardware Description Language that push Verilog into the systems space and the verification space and was built on top of the work of the IEEE Verilog 2001 committee.

SystemVerilog 3.0 is built on top of Verilog 2001 and improves the productivity, readability, and reusability of Verilog based code. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

Providing insight as to why Co-Design would make such a deal, Gary Smith, chief EDA analyst at Gartner Dataquest said that Simon Davidmann, CEO and co-founder of Co-Design was trying to leverage the standards process to gain a critical advantage for his tools. SystemVerilog 3.0 contains Superlog constraints.

Looking at the primary list of contributors for SystemVerilog 3.0, Co-Design has a large interest represented; Vassilios Gerousis, Dave Kelf (vp of worldwide marketing for Co-Design), Stefen Boyd, Dennis Brophy, Kevin Cameron, Cliff Cummings (Co-Design investor), Simon Davidmann (CEO and co-founder of Co-Design), Tom Fitzpatrick, Peter Flake (CTO and co-founder of Co-Design), Harry Foster, Paul Graham, David Knapp, Adam Krolnik, Mike McNamara, Phil Moorby (chief scientist of Co-Design), Prakash Narian, Anders Nordstrom, Rajeev Ranjan, John Sanguinetti, David Smith, Alec Stanculescu, Stuart Sutherland, Bassam Tabbara, and Andy Tsay.

Another blow to Co-Design occurred at DAC2002, when Synopsys offered all of its testbench standards to Accellera, which pulled the rug out from Co-Design for that leverage, Smith added.

Since it likely saw that it lost its advantage, combined with the inability to raise sufficient operating capital, it is possible Co-Design decided to throw in the towel as an independent company and instead allow the technology to live on in SystemVerilog.

--Ann Steffora, Managing Editor

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