WILSONVILLE, Ore.—(BUSINESS WIRE)—May 14, 2007— Mentor Graphics Corporation (Nasdaq: MENT) today announced it has expanded the comprehensive Questa(TM) verification solution, which combines tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today's designers. The announcement includes the new Questa 6.3 functional verification platform addressing low-power verification, and powerful verification management capabilities that enable closed-loop management reporting, analysis and documentation. It also includes improved debugging and version 3.0 of the industry's first open-source standards-based Advanced Verification Methodology (AVM).
"Power and complexity are the two design drivers that are
impacting today's verification flows," said Robert Hum, vice president
and general manager of Mentor Graphics Design Verification and Test
division. "Complexity is also an increasing issue with tool
environments. With the Questa 6.3 functional verification platform,
we're solving these issues by delivering the critical new capabilities
required by today's designers while simultaneously eliminating many of
the tool and integration issues that complicate today's flows. The
combination enables the increase in productivity that teams need to be
successful with today's designs."
Verify Low-power Behavior in RTL
Effectively managing power consumption is a critical design issue
in many markets. The increasing size of today's designs has made
traditional post-place and route insertion and verification of
low-power design techniques such as power gating and retention
impractical. The Questa 6.3 functional verification platform includes
new simulation technology that enables verification of power control
logic at RTL (register transfer level) before synthesis when it is
easier to validate and repair issues in the system power architecture
With Questa 6.3, designers can specify low-power design intent
without modifying their RTL code - reducing any costly re-verification
of existing intellectual property (IP) blocks. Questa 6.3 accurately
simulates shutdown and power-up behavior to verify that the chip
operates as intended in all system power states. To support the common
use of retention in today's designs, Questa 6.3 allows the easy
specification of retention capabilities with inferred flip-flops and
latches as well as memories in the RTL design. These features enable
identification of difficult bugs such as the interaction of register
clock and reset signals with the save, restore and retention states
early in the design cycle.
Mentor Graphics supports the Accellera Unified Power Format (UPF).
The Questa Power Configuration File was donated to Accellera and was
used in the development of this new industry standard that offers
portability of low-power design data and interoperability of tools in
a low-power design flow.
Comprehensive Closed-loop Verification Management Delivers
Designers are faced with massive amounts of data from their
verification tools. Getting actionable information from this sea of
data is the key to verification productivity. The Questa 6.3
verification platform features a verification management toolset that
includes a Unified Coverage Database (UCDB) that collects and manages
all verification data, automatic import of verification plans written
in Microsoft Word and Excel and XML, and a tracking and reporting
system that closes the verification loop by delivering coverage
information mapped to the verification plan.
Questa Verification Manager optimizes the verification process by
identifying redundant tests, tests that achieve a specific purpose -
highest coverage within a given amount of simulation time or tests
that hit specific coverage areas - and the functional areas that have
not yet been verified. These actionable metrics enable verification
teams to improve efficiency and reduce time to coverage.
Improving Debugging Reduces Repair Times
The bottleneck within verification is the time it takes to analyze
and resolve bugs. Questa 6.3 introduces new capabilities to speed the
debug process including graphical and source-based traceability of
incorrect results to their root cause and an innovative assertion
debug capability. Questa's Assertion Thread Viewer provides a
graphical view of the evaluation of an assertion or coverage property
from initial activation until final pass or failure. This
functionality provides all the information needed to understand why an
assertion passed or failed as well as improving the quality of
assertions by identifying poorly written properties that can severely
impact simulation performance.
AVM 3.0 Extends First Open Source Verification Methodology
The Mentor Advanced Verification Methodology (AVM) is the first
true system-level-to-RTL verification methodology. The AVM integrates
advanced verification techniques like constrained-random stimulus,
functional coverage and assertions into a single transaction level
modeling (TLM)-based framework implemented in both SystemC and
SystemVerilog. All AVM libraries are available in source code format
in both SystemVerilog and SystemC. AVM 3.0 now includes improved
management and reporting features, more top-level environments for
integrating 3rd-party IP and a revamped Verification Cookbook - the
AVM end user manual - that includes new material on object-oriented
programming and working with modules.
Product Availability and Pricing
The Questa 6.3 verification platform will ship in Q2 2007 and
includes access to the Advanced Verification Methodology portal.
Configurations start at $24,000 USD for a 12-month license. AVM 3.0
will be available in Q2 2007 at no charge under a standard,
open-source license. For additional product details, call
1-800-547-3000 or go to www.mentor.com/questa.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:
MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$800 million and employs approximately 4,250 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777. World Wide Web site:
Mentor Graphics is a registered trademark and Questa is a
trademark of Mentor Graphics Corporation. All other company or product
names are the registered trademarks or trademarks of their respective