Renesas Introduces Dual-Core 32-bit SuperH Microcontrollers Capable of Up to 960-MIPS Processing Performance, 800 MFLOPS Floating-Point Operation Performance

SAN JOSE, Calif.—(BUSINESS WIRE)—April 23, 2007— Renesas Technology America, Inc. today announced five new SuperH(R) 32-bit microcontrollers that use multi-core technology to achieve the high levels of performance required by many embedded system applications such as consumer products, industrial equipment, and car audio and navigation systems. The SH7205 and SH7265 devices incorporate two superscalar SH2A-FPU CPU cores and a comprehensive set of on-chip peripherals that includes USB, ATAPI, and image processing engine functions. When the dual-core microcontrollers are operating at their 200 MHz maximum operating frequency, each CPU delivers 480-MIPS (million instructions per second) processing performance in the Dhrystone v1.1 benchmark, and 400-MFLOPS (mega floating point number operations per second) floating-point operation performance.

To meet inevitable demands for higher functionality and performance, the new microcontrollers use a design approach fundamentally different from the traditional method. In the past, generations of ever-finer process nodes have been used to improve integration density and increase operating speed. Today, however, semiconductor technology has reached the point where it takes considerable time to develop finer manufacturing process nodes. Moreover, fundamental limits of physics now mandate design solutions for an expanding variety of difficult problems, such as increased leakage current.

To avoid these problems, Renesas developed a multi-core architecture for microcontrollers used in embedded applications. One of the main benefits of putting multiple CPU cores in a single chip is increased device performance because the CPU cores can execute lines of software code in parallel. The multi-core ICs for embedded systems previously introduced mostly have been aimed at image processing and similar multimedia products with heavy processing loads. By contrast, the SH7205 and SH7265 microcontrollers are general-purpose devices that target a broad span of applications requiring high-speed real-time control and processing performance equivalent to that of a digital signal processor (DSP) chip.

Multi-core architecture

The multi-core architecture of the SH7205 and SH7265 microcontrollers makes it possible to achieve high levels of performance while offering flexibility of use. The microcontrollers implemented a solution in which real-time processing performance does not degrade as processing becomes more complex and faster. The three main technologies in the CPU core's design are:

-- The internal bus system uses a CPU-specific multi-layer structure. A 4-layer configuration provides two layers for CPU use and two for DMAC (direct memory access controller) use. This prevents time from being wasted while the bus is in use by the other CPU, for high-speed real-time processing.

-- The CPU cores can operate on different operating systems (OSs) or the same one. If one CPU core runs the uITRON OS, while the other runs the uClinux OS, for example, they can execute completely different programs. This capability lets engineers construct a system flexibly, according to its use or purpose.

-- The two CPU cores can communicate directly with each other. Each CPU can check the status of the other one, and they can exchange data using memory provided for that purpose. Thus, processing linkage can be implemented between the CPUs through mutual exchanges of their respective processing states and data.

On-chip peripheral functions

The extensive array of peripheral functions built into the SH7205 and SH7265 chips reduces the need for external parts and enables to create high-performance systems at less cost. They include a USB v2.0 High-Speed (480-Mbps) specification interface, ATAPI interface, and other various interfaces. The devices have a 2D graphic engine and a digital video input pin for graphic processing, and has WQVA-size (480x234-pixel) and QVA-size (320x240-pixel) analog RGB output pins for image and video output processing.

Other on-chip functions include a 5-channel multifunction timer unit (MTU) suitable for motor control systems, 2-channel CAN controller, 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, watchdog timer (WDT), 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications, and more.

Besides these functions, the SH7265 provides an encoding accelerator for AAC (Advanced Audio Coding) as the audio data compression method. This function can be used for high-speed hardware implementation of music data or similar AAC file creation.

System development tools

Customers can use currently available compiler, assembler, and linker products as a system development environment for the SH7205 and SH7265 microcontrollers. Additionally, Renesas is developing an enhanced version of the E10A-USB emulator with multi-core support and a dual-core OS, the uITRON HI7200/MP. This OS has an inter-CPU communication function that eases the implementation of application software and enables current software resources to be used in dual-OS operation.

Price and availability
                                   Maximum
                                  Operating
                                  Frequency
                                  (Operating Differences    Sample
                                  Temperature in On-Chip     Price/
Product Name          Type Name     Range)     Functions  Availability
----------------------------------------------------------------------
SH7205             R5S72050W200BG   200MHz       None         $21/
                                  (-20 to 85               July 2007
                                  degreesC)
----------------------------------------------------------------------
SH7265             R5S72650P200BG   200MHz      -- AAC        $22/
                                   (-40 to      encoder    July 2007
                                  85degreesC) accelerator
                   --------------            -------------------------
                   R5S72651P200BG               -- AAC        $23/
                                                encoder    July 2007
                                              accelerator
                                             -- SD memory
                                                 card
                                                       interface
                                      --------------                        -------------------------
                                      R5S72652P200BG                              --  AAC                $23/
                                                                                                encoder        July  2007
                                                                                            accelerator
                                                                                              --  IEBus
                                                                                              controller
                                      --------------                        -------------------------
                                      R5S72653P200BG                              --  AAC                $23/
                                                                                                encoder        July  2007
                                                                                            accelerator
                                                                                          --  SD  memory
                                                                                                  card
                                                                                            interface(1)
                                                                                              --  IEBus
                                                                                              controller
----------------------------------------------------------------------

(1)  An  SD  card  license  must  be  obtained  in  order  to  use  the  SD  memory-
  card  interface.
 


1 | 2 | 3  Next Page »



Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise