Calypto's SLEC RTL Product Selected by AMD to Verify Advanced Processors

SANTA CLARA, Calif.—(BUSINESS WIRE)—March 14, 2007— Calypto(TM) Design Systems Inc., the leader in sequential analysis technology, announced today that AMD (NYSE:AMD), has adopted its SLEC(TM) (sequential logic equivalence checking) product into its microprocessor design flow.

AMD chose SLEC RTL software to verify performance and power optimizations in its advanced microprocessor design flow.

The SLEC RTL product comprehensively verifies sequential optimizations, such as RTL retiming and clock gating which are typically performed in microprocessor design flows. SLEC uncovers design differences in short concise waveforms, simplifying error detection and reducing debug time from weeks to days.

"Our microprocessor design teams are consistently innovating to increase overall performance and deliver industry-leading performance-per-watt," says Nihar Mohapatra, design verification lead, AMD. "The fast, comprehensive verification which Calypto's SLEC provides enhances this creative process, helping our design teams continue to meet the processing needs of our customers."

AMD's leading-edge processors feature AMD's Direct Connect Architecture, which helps eliminate the bottlenecks inherent in a front-side bus by directly connecting the processors, the memory controller and the I/O unit to enable improved overall system performance and power efficiency. The AMD Opteron processor is the only x86 server processor with planned upgradeability to native quad-core within the same thermal design power envelope. Upcoming native Quad-Core AMD Opteron processors (codenamed "Barcelona") are estimated to provide a 40-percent performance advantage over the competition, and will enable new power- and thermal-management techniques, strengthening the industry-leading performance-per-watt AMD Opteron processors currently deliver today.

SLEC is the semiconductor industry's only Sequential Logic Equivalence Checking solution that can verify functional equivalence between designs with sequential differences. Also part of the SLEC product family is SLEC System, which verifies that RTL implementations functionally match System level models written in SystemC or C/C++. The SLEC product family is based on unique sequential analysis technology that bridges levels of design abstraction, Enabling ESL(TM)

Commenting on SLEC's success and market adoption, Tom Sandoval, Calypto's chief executive officer, remarks: "It has become extremely difficult to meet both power and performance targets using traditional gate-level methods. To achieve design goals, hardware engineers must make micro-architectural changes to their RTL. Using SLEC, design teams can create higher quality designs in less time."

About Calypto

Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving customers millions of dollars in design costs and avoiding silicon re-spins. Calypto delivers design software products to leading-edge semiconductor and systems companies worldwide. Calypto is privately held, with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, and the Mentor Graphics OpenDoor program. Corporate Headquarters are located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: More information about Calypto may be found at:

Calypto and SLEC are trademarks of Calypto Design Systems Inc. AMD, the AMD Arrow logo, AMD Opteron, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. Other products and company names may be trademarks or registered trademarks of their respective companies.


Public Relations for Calypto Design Systems
Nanette Collins, 617-437-1822
Email Contact

Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Sr. staff ASIC Design Engineer -2433 for Microchip at San Jose, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy