Fast-SPICE with Nascentric


The former Nascentric CEO, Vess Johnson, has moved over to VP of Consulting Services. Was Nascentric looking for a new CEO?
Yes. The Nascentric board went out seeking a new CEO. That’s’ how I started talking to Nascentric. Sometimes it happens. Startups in general are tough and EDA startups are even harder. Vess is a great mentor to the team. He is very valuable to the team. He is adding huge value now in the role he is playing. This is like a symphony orchestra. Everybody has a role to play. The board of governors has appointed me to be the conductor.

Nascentric is in the Fast-SPICE market. How would you define the Fast-SPICE market?
Traditionally SPICE is by default the simulator that people trust. Silicon vendors, chip designer all trust SPICE simulation for the accuracy of its models. The problem is that SPICE was built in 1960. It is very slow. It is great if you have 50 to 100 transistors you want to simulate. But nowadays there could be millions of transistors. If I want to calculate IP, lets say an IP vendor like Qualcomm, nobody is building everything from scratch. They are buying IP blocks. They are acquiring or they have already built it themselves. 80% of the new chip is pretty much the same as the old chip. They do the interfaces. If you look at the IP market, look at SRAM or some custom digital designs you can not use SPICE. It does not work. What they do is they have what is called a cut netlist.

If you want to simulate the whole SRAM, you can not do it today. It is millions of transistors. So they cut the netlist. They characterize what would be worse case paths. They’ve got some heuristics and other things that people use but it is still an approximation. With Nascentric you do not have to cut the netlist. Just simulate the way you doing because our simulator can run so much faster and has so much more capacity. We can easily simulate SPICE runs out of stream at 20,000 equivalent transistors.

Dennis: Some of what we are hearing from a lot of IP vendors is that even the cut netlist is presenting tremendous problems in the design process itself because at 65 nm there are so many more parasitics that even cut netlist has so many devices in it that it is causing problems as well. They really need a simulator that we traditionally think of as a Fast-SPICE simulator, able to handle all the parasitics, all the devices and able to simulate that accurately enough so that accuracy is not lost due to people having to throw things away in the traditional flow.

You know that the Nascentric product has been delayed. It is amazing technology. I am pretty excited abut it. Some of the good stuff we are working on will actually lend itself to Fast-SPICE simulation, 1000x faster than SPICE and be able to handle the capacity of millions of transistors, capacitors and resistors, all the RC effects and at the same time have accuracy with plus or minus 2 or 3 percent of SPICE. That’s what we are trying to offer in our product line. Frankly there are other products in the market today. We are not the only one. But we have some differentiators that we believe will be extremely interesting too the customer base.

Who are some of these other vendors and what are the differentiators?
Dennis: If you think about the Fast-SPICE market, it is divided up into Synopsys, Cadence and Magma has also entered the market as well. Again the real issue is that what those guys really have is a traditional SPICE simulator. It is an engine that is based upon SPICE itself. SPICE has not changed in 30 years.

What they have done for the most part is that they have figured out better data management strategies or they have figured out ways to throw away more parasitics so that they can get the performance and the capacity they need. What we have done with AuSIM is a different approach. The technology is based upon being able to do a better job of modeling unique devices so we basically have a multi-engine architecture. That means we create special models and engines to operate on transistors differently than on interconnects or operate on the transistors differently than on a slightly larger sub-block or cell type of entity. Because we manipulate things that way we have the ability to optimize the data is represented in the data structures and the way it is manipulated in terms of the calculations for the simulation itself. We get a much more accurate result and we are able to simulate faster. The key differentiator is really being able to run the simulation much faster than the competition as well as having the architecture that allows us to take advantage of new technologies that are on the horizon such as multiprocessor and multicore machines as well as the capacity that is required to handle all the additional parasitics. Not too long ago you may have seen that we were awarded several patents for the way we are modeling those devices. We should be announcing additional patents shortly.

Nascentric AuSIM’s Multi-engine Architecture


The product was originally called Nascim but was renamed AuSIM. Any significance or just some marketing guy with a cute idea?
Denis: A couple of reasons. One is the feedback from customers was that we needed a more appropriate name. We needed a name change to make sure we were clearly differentiated from the name of other simulators in the market.

Rahm: What Denise is trying to allude to is that Synopsys had a product called Nanosim. NanoSim is close to Nascim. That’s not what we wanted. We wanted something different which is why we changed the name. Au stands for gold. Au also stands for “Awesome” simulator. Further some of the technology comes from Austin, Texas. It is really an awesome simulator, a play on words.

You said that there was a new release or a next generation version of the product that has been delayed. Can you describe the feature set and the performance as well as the timeframe for its availability?
We have several beta sites evaluating the next generation system. We alluded to that in an interview a couple of weeks ago. In the next 6 to 8 weeks we will announce the product. Right now we take in the SPICE netlist and do what we call an intelligent topological assessment. We analyzed that this is a transistor so let’s use the transistor engine on this. Here is an interconnection

In sub 65nm if you want to analyze a post layout netlist, oh my god, it is dominated by RC delays and all the stuff that is going on. What we have is a transistor engine, an interconnect engine, a cell based and block based engines. Once we compress the topology we apply different focused engines. Here is where we differentiate from SPICE. SPICE does not do that. Each of these engines will operate on its own. With all the new technology coming out in the marketplace we will be able to leverage those resources. We want ot be in the Fast-SPICE market. Obviously, we want to be much faster than the competition for us to be considered and we need to be able to handle the capacity and be able to be plus or minus 2% to 3% of SPICE. We are very close to announcing that.

I am being cagey not to give you the details because we want to talk about it once the product is out of beta. Then we can talk about some of the customer successes.

The company is headquartered in Austin and yet you are located in San Jose.
I am in between. We have an office in San Jose. We are going to add primarily outbound application engineering as well as good engineering talent, if we can find it here. I am going back and forth between the two places. I take the usual Austin flights back and forth. Every other week I will typically be there.

Has there been any additional funding associated with your coming on board?
Yes. We have already added $7 million so far. We are trying to get even more. We have not announced it yet. We have not closed on the funding yet. We are still working on a few things. It will help us to sustain development as well as expand the sales footprint. As we go to market there will be a need for cash.

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