Fully-Integrated DDR3 Register Simplifies Design, Saves Power and Board Space
Manufactured in TI's 130-nm process technology, the SN74SSTE32882 also integrates a high-performance, low-skew buffer with the register and low- jitter PLL. Integration of the PLL eliminates the need to tune the memory module, greatly simplifying design and board layout to accelerate server and RDIMM manufacturers' market entry. Customers can also enjoy improved performance and reliability with the integration of these features.
The SN74SSTE32882 28-bit 1:2 configurable registered buffer is designed for 1.5-V VDD operation for high speed and low power consumption. One device per DIMM is required to drive up to 36 SDRAM loads. The edge-controlled circuit outputs meet SSTL_15 specifications and are optimized for terminated DIMM loads. To provide maximum flexibility and support industry-standard DIMM configurations, the clock and control outputs can be programmed with differing drive strengths.
The SN74SSTE32882 fully supports parity features as defined by Joint Electron Device Engineering Council (JEDEC). This parity function improves reliability of server systems. The SN74SSTE32882 also supports spread spectrum clocking (SSC) to reduce EMI.
"The SN74SSTE32882 is the first device on the market enabling the future of cost- and power-efficient registered DIMMs for next generation servers and high-end PCs," said Kent Novak, general manager of TI's high-speed communications group. "This device is a result of TI's analog technology leadership and cooperation with industry-leading chipset vendors, server OEMs and DIMM manufacturers."
Information on available DDR3 RDIMMs and the complete line of clock products from TI is in the Clocks and Timers Selection Guide, available at http://www.ti.com/clocks .
The SN74SSTE32882 is packaged in a 176-pin BGA with 0.65 mm ball pitch in an 11 x 20 grit. It is sampling today and will be in full production in 3Q2007.
About Texas Instruments
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