Whenever one speaks of Standards, comments one hears are:
"So many standards for the same thing." "Standards stifle competition" "Committees produce to little, too late"
This viewpoint tries to explore EDA standards. I’ll start with conclusion and move backward touching upon need for standards, problem with standards, some standard/format wars and standard bodies related to EDA
The design community has been clamoring for interoperability solutions so that it can focus on solving complex design problems, not on procuring and developing translators, syntax checks and other inefficient workarounds.
EDA companies had historically developed and marketed tools based on their own closed propriety design languages. That approach limited invocation, fosters small and fragmented niche markets, lengthens time to market, imposes inefficient learning curves on designers and imposes substantial risks to customers
The key lesson learned by the EDA industry from the language wars is that adoption of languages is driven by standards. Designers want and need interoperability and design flows that work with them and not against them. To that end, the user community, EDA vendors, standards organizations such as Accellera, and the IEEE have worked together to create a set of language standards that meets the demands of designers today and into the future.
Though we don't yet know which of the standards are destined to change the course of EDA, one thing is clear: Standards in general have the capacity to serve both vendors and users well, and the coming years will continue to witness more and more efforts to gain control over the explosion of EDA tools and work flows for the ultimate benefit of designers worldwide. Competition is good for every industry and finally customers decided which standard is adopted.
Standards/Languages are a necessary starting point. Methodology enhancements will be focal point.
Need for Standard:
The design landscape is growing more diverse, featuring interfaces that are simultaneously becoming more numerous but also more complex.
The advent of new process technologies has raised new hurdles to block the design process. Interoperability of IP, tools and libraries is a global issue.
-Help ease the task of assembling a workable EDA Design flow.
-Are needed for ensuring tools' interoperability and fair competition.
EDA standards can be classified into following three categories:
a) User to tool i.e. design languages
b) Tool to Tool such as EDIF
c) Tool to physical such as ASIC libraries
Problems with Standards:
1) In each standard there has to be clearly defined subsets for tools/design stages they are aiming. This is not the case at the moment.
-Still even within the VHDL standard "gray areas" are found i.e. there are different interpretations.
-In some cases it is also seen that tools support "de-facto" subset not the whole LRM or some parts against LRM ex Verilog for Synthesis
2) Standards should be more compact and clear
-Tools support for whole standard is needed.
-Standards need to improve productivity and quality.
How do Standard come into existence:
Standards can take many paths
1) Formats begin in proprietary format that flourish design flows. Some de-facto standards are later contributed for continued industry driven growth through standard bodies, for example Verilog. Other propriety standards diminish when an open effort duplicates its functionality without restrictions on use.
2) When technology is not readily available standards are developed to meet designer’s need and encourage their use to ensure adoption for example System Verilog.
Committees are formed to investigate and standardize the format.
-Typically they employ proven technology, form efficient technical subcommittees to review technology contribution
-They work in partnership with the corporate move
Mission is to provide the standards and consistency for rapid design to market.
Hours of dedicated discussion and debate, research, and response are put in to create unbiased standards that work.
Some of the Standard Groups are:
-The IEEE Design Automation Standard Committee (DASC) is responsible for the standardization of Design Automation related standards in the IEEE.
-Accellera: Formed by merger of Open Verilog International (OVI) and VHDL International (VI) in 2001. Its Accomplishments:
Verilog and VHDL Language Development & Adoption
Formal Verification - Property Specification Language
RTL Synthesis Interoperability Standards
Verilog Analog/Mixed Signal Language.
- Silicon Integration Initiative (Si2) is an organization of industry-leading companies in the semiconductor, electronic systems and EDA tool industries. It was formed in 1988.
-Virtual Socket Interface Alliance (VSIA): It creates standards for system-on-chip Virtual components (blocks of intellectual property)
Changing face of Standard:
Typically standards are implemented using ASCII files. However Application Programming Interface are slowly becoming the preferred approach.
Methodology is the answer:
Languages are a necessary starting point, and to a large extent, have evolved to being competent in terms of specifying the functionality. Where there once were 'language wars,' languages aren't really the focal point today. The battle is over how to get the fewest functional errors at the end of the process. Languages alone won't solve it. Methodology enhancements are the answer. For example in DAC held this year, PANEL discussion was on the ESL methodology
Standard wars happen in other domains:
Standard/Format wars are not unique to EDA. For the next generation of DVD chipsets, format war is on going. DVD has been the fastest consumer electronic product and has been terrific earner for many design houses and semiconductor manufacturers. Toshiba, NEC, Sanyo Microsoft and Intel are supporting HD-DVD while Sony, Philips, Matsushita, LG Electronics, Samsung and JVC are supporting Blu-ray.
Standard Wars in EDA:
Verilog and VHDL
When the topic of design languages comes up, most industry veterans think back to the "language wars" of the late 1980s and early 1990s. Back then, VHDL and Verilog vied for dominance, with numerous other proprietary hardware description languages (HDLs) nipping at their heels.
For details on Verilog and VHDL war, one can go through my document “EDA story so far”
SystemC & SystemVerilog
Two languages on most designers' radar screens for System Level Design are SystemC and SystemVerilog. Now, who uses which, and why? Also, can SystemC and SystemVerilog coexist in the same flow?
The unfolding consensus is that the languages are indeed complementary. "Where it's evolved to today is that SystemVerilog is a great means to extend Verilog to provide what designers really need," says Novas' Dave Kelf. "It's done in a simple fashion but in the HDL world. So they're using it for extending design and adding simple verification structures, and I think that's its sweetspot. SystemC, on the other hand, is very much focused on systems and software."
A number of standalone verification languages arose in recent years. Most prominent among them are Verisity's (now part of Cadence) e language and Synopsys' OpenVera. OpenVera was donated some time ago to Accellera, and most of its attributes are now incorporated into SystemVerilog 3.1a. There's a good deal of both e and Vera legacy code that many designers still turn to when evaluating IP for integration. Verisity's senior vice president of marketing, Steve Glaser, emphasizes what he terms the "vertical role" of e in the verification process.
GDSII and OASIS
Oasis is an advanced, IC-to-mask layout data transformation standard owned and maintained by SEMI, which supplants the GDSII stream as the data output to mask shops from IC design. While the GDSII database format has long been the route designs took so that mask writers and pattern generators would recognize the design data, the industry has known for some time that GDSII is running out of steam accepting only 16-bit and 32-bit files.
Its effort began in 2001. Oasis Translator was launched in Sep 2002 and ratified as a SEMI standard in September 2003.
EDA Standards for the Millennium. by Steven E. Schulz
Getting To A Higher Level: