MathWorks: Simulink HDL Coder

I talked about the limitations of FPGA vendor products. They are still quite a powerful tool and very useful when customers want to use their IP cores directly in the design. You can take our generate code and their generated code, import them through the black box mechanism and create something which includes the entire design.

A number of board vendors are working with this tool now to come out development solutions that will allow a complete flow from the MathWorks product down into an FPGA board where you can test in real time and get rapid feedback.

One important aspect of model based design is the use of the model itself as the testbench. Once you have tested the model components to be bit exact and cycle accurate and once you have done the implementation whether it is automatically generated or even hand coded, you can use that model to test it rather than rewriting additional testbenches in the hardware description language. When you do that, you can apply certain system level metrics to determine whether the implementation has degraded the design in any way or varies from the specification.

The functional verification actually runs faster, the simulation runs faster because only that particular component is running at the RTL level of detail. Everything else is at the higher system level and therefore runs much faster. Another benefit is that multiple engineers working independently can verify their components not only at the component interface level but at the system level by plugging it back into the overall system model. The generated HDL code can also be used with downstream third party tools, for example other methods for verification.

What was the feedback from your beta test?
We covered the world with our beta test with 60 customers from a variety of industries such as semiconductor, wireless, automotive and aerospace. There were both ASIC and FPGA projects. We are getting very strong and consistent feedback that the product is a critical element for the acceleration the development process because it is automating this aspect of the design process.

Simulink itself has a better environment than C code which is still used as a starting point for system design. In terms of sharing information among team members especially when they are in different locations, you can understand the behavior and design intent of colleagues much better using a Simulink model than by looking at their C code.

The person from Agere Systems cited in the press release said that they see the most important benefit to be the ability to perform multiple iterations on the design done very quickly. Each individual block element may not be optimized to the extent a hardware designer might be able to realize but the overall system they can try different architecture, explore various options and arrive at something that meets the requirement much more quickly because they can experiment and explore so rapidly.

There are 60 beta sites but only one is named in the press release.
We have a couple of others we hope to have. Getting through the approval process can sometimes be time consuming. We are hopeful that we will have approval from their corporate PR guys at few others.

What is the pricing and packaging fro HDL Coder?
The product is available immediately and on the three platforms (Windows, UNIX and Linux) that are typically used for FPGA and ASIC design. The price is $15,000 for an individual perpetual license which includes the first year of maintenance service. In subsequent years you pay a percentage of the initial price for maintenance. This service includes technical support and updates.

Individual license means node locked?
Yes. We also have a concurrent license that can be shared across a network. In some cases we have annual options. Typically this is for larger configurations. We generally do not offer that on an individual license basis. But when there is a site or work group, we can offer that as an option. The specific price would depend upon the configuration. Each customer has to do their multiyear cost of ownership calculation to see what is best for them.

The required products include MATLAB and Simulink and the products that enable fixed point computation within each of these products. There are also a number of recommended products that add functionality either in terms of additional algorithmic blocks and in the case of Stateflow finite state machines or in the case of Link to ModelSim this co-simulation or black box import capability.

What would be the cost for a perpetual license of the required products?
That would be $6,700 for those four products, so a total of $21,000.

What is the usage model of HDL Coder relative to Simulink? Does one bounce back and forth or does one only occasionally launch HDL Coder?
It depends upon the task. If you are working on a particular component or subsystem, if you are trying to explore the architecture and get the right design for that subsystem, you would tend to stay in Simulink most of the time. You would use the automated scripts to invoke the synthesis tool to gain insight into the final implementation in terms of area, clock rates and the like. But you don't need to interact with the synthesis tool to do that. You are getting the results out to determine whether it is good enough and whether you need to iterate and try a different design approach. That would tend to be staying in Simulink.

On large projects when you are integrating multiple components there are likely to be different engineers some of whom would tend to spend more of their time in the HDL simulation environment and others who would stay in the Simulink environment. During the course of a project it is going to be back and forth. During the design of a particular component I would expect it would be heavily staying within Simulink.

Could say three engineers who were using Simulink on a daily basis effectively share a single copy of HDL Coder or would they each need their own copy?
It depends on where they are in their project cycle. They may need multiple copies of Simulink and fewer copies of this product. That's one possible scenario where this product would be used less frequently. It might be used all the time during certain phases of the project. But there are other phases where it would be used less frequently. We have seen that with our C code generation product where there are phases where you are doing the initial specification and simulation work, you are not really doing code generation until you get to the prototyping phase. That's likely to happen with this as well. There are going to be cycles in this project which will require more use of this product. It depends upon what the design looks like. If there are several engineers working on components, digital hardware components, then you might need one for each of them. If some are doing hardware, some doing software, and some doing analog or RF design, then only a subset will need it. Sorry I can't give an exact rule of thumb.

How would you summarize?
The key points in terms of impact of this product are: First being able to use a single Simulink model for both hardware and software. The ability to do design work and develop IP that is technology and device independent. Direct generation of hardware description language from the Simulink executable specification bridging the most commonly used system design tools with the standard hardware description languages. Connecting not only the tools but facilitating communication between the different sets of engineers.

Who is the competition for MATLAB and Simulink in the market you are responsible for?
The primary competition is C code. A lot of people are writing their own C code. If the origins are in the R&D department and algorithm developers, then there are a variety of math packages that are sometime used. As you get more into system level design there are a few tools like Signal Processor Design that used to be called SPW. There is also Ptolemy and a few others that are used for some aspects. The Agilent products tend to be more in the RF end. The SPW product is focused a bit on some of the wireless applications. It doesn't have the breadth of multiple domain capability that Simulink does.

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

Review Article
  • October 09, 2008
    Reviewed by 'Mike'
    Hello Jack:
    I read your articles and I appreciate the depth to which you probe the various subjects you cover. In your recent article in which you interviewed Ken Karnosfky, Director of Signal Processing and Communication at MathWorks, I believe you missed uncovering HDL Coder's (HDLC) most significant competition which I think your readers would benefit knowing about.
    I should mention I am a sales manager for Synplicity, and my geographical responsibility is the central US. Synplicity has a product in the exact space as HDLC, called Synplify-DSP. It interfaces to Simulink and it outputs vendor and technology independent, synthesizable RTL. It has been on the market for 2 years and is doing well. EDACafe carried the tool's introductory announcement ( which included a quotation from Ken Karnosfky in support -see next paragraph below.
    "DSP designers are increasingly targeting FPGAs for implementation of high-performance DSP designs," said Ken Karnofsky, marketing director for DSP and communications products at The MathWorks. "Synplicity has delivered sophisticated tools for users to generate high-quality RTL code from Simulink that not only delivers impressive QoR, but leverages the comprehensive DSP simulation and analysis already built into Simulink."
    Synplify-DSP is the only tool offering true synthesis of the Simulink model (automatic folding, pipelining, multi-channelization, polyphase decomposition) and we uniquely offer technology specific RTL output, which is optimized for high quality of results and can be retargeted with the push of a button. We have several public success stories to date ( for one). The tool has come a long way since it's introduction and we continue to improve the tool with each release, recently adding M-code control logic description support, vector support, and RTL import support for example. A simple Google of Synplify-DSP will yield many related, informative links if you are interested.
    I know the focus of your article was HDLC and it is good to raise awareness for this tool specifically, and DSP development flows in general. There are several options for the designer to consider and Synplify-DSP is certainly one of them.
    Thanks for listening. I'll keep reading.
    Mike Lux
    Central Area Sales Director

      5 of 7 found this review helpful.
      Was this review helpful to you?   (Report this review as inappropriate)

For more discussions, follow this link …
Featured Video
More Editorial  
Upcoming Events
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
SEMICON West 2017 at Moscone Center San Francisco CA - Jul 11 - 13, 2017
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017
NEC: CyberWorkbench
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy