"The MTBSolutions Ultra-Flat Package Technology enables the management of stress fields around low-k dielectrics," stated Mark DiOrio, CEO of MTBSolutions. The Ultra-Flat Package Technology is believed to be both a technical enabler and may also be a cost enabler. It is primarily utilized for large scale flip chip packaging structures where package flatness and the corresponding stress transmitted to the Si chip is of concern.
The Ultra-Flat Package Technology was developed for FC-BGA where the CTE dissimilarities between the silicon chip and the organic substrate result in a package warpage inducing undue stress upon the FC interconnect structure. The technology is designed to:
-- Reduce package warpage by 50% over current processes -- Improve flip chip interconnect reliability by a factor of 2X -- Reduce low-K ILD cracking in the silicon chipUltra-Flat Package Technology is a series of patents that include both processing and design methodologies designed to reduce stress between the organic package and the silicon die which can be detrimental to the reliability of the flip chip interconnect joint and the silicon chip's inner layer low-K dielectric.
The first series of patents covers the methodology of applying the underfill material between the substrate and the silicon chip after FC interconnect. This methodology can be used with the existing material sets without an increase to cost. In some cases further improvements have been seen with the selection of alternate underfill materials. These underfill methodologies have yielded results showing as little as 2 mils package warpage when measured diagonally on a 40X40 mm package size as compared to more standard processes yielding as much as 4 mils on the same package size.
The second set of patents cover the methodologies of heat-sink/stiffener attach and underfill to reduce the level of package warpage. These are in combination to the above patents of underfill dispense methodologies.
The third set of patents pertains to the design methodology of the FC-BGA pads to match the silicon pads at operating temperature. By reducing the stress on the FC interconnect structure between the silicon chips to organic package, device reliability can be significantly improved.
MTBSolutions, Inc., a San Jose, California-based company, is the world leader in advanced microelectronic packaging and test technology for semiconductor, photonic and MEMS applications. MTBS clients include device makers, subcontractors, material suppliers, and foundries. For more information, visit www.mtbsolutions.com
Contact Information: Brian F. Brackle MTBSolutions, Inc. +1.408.728.0827 Email Contact Mark DiOrio MTBSolutions, Inc. +1.408.570.9711 Email Contact Jon Carvill AMD Corporate Communication +1.512.602.1000 Email Contact