Calypto - Equivalence Checking

What is the pricing of these products?
The pricing starts at $175K per year term based licensing and goes up to $250K based upon options. Basically the lower end of the range is for SLEC RTL product and the higher end for SLEC System, the more advanced product. When were these product introduced?
The first version of the product was announced in April 2005 when our first two customers, Renasis and FreeScale, officially started using it. We just announced version 2.0 a few weeks ago. It is a much improved product in terms of capacity and runtime. We have added more customers: STMicro, TI and Canon. We are currently working primarily with the top twenty semiconductor companies. We believe that they are the ones applying new methodologies, ESL methodologies, to create new and more efficient flows.

How many seats would the typical customer purchase?
Our primary customer is really the RTL verification engineer rather than the architectural designer. What happens in typical cases where our customers get into trouble is that they have RTL they have to verify. They really don't have a testbench that is suitable for that RTL. In this case of the microprocessor design for example, they had a testbench that worked for the original RTL but the new RTL after they applied power transformation and so forth are substantially different from the old RTL. So the old testbench does not apply. The RTL verification engineer now has a problem to verify the new RTL. In the case of these two customers their only choice was to run system level simulation which could take 2 or 3 weeks to complete. Then if there was a bug at that point, it is very difficult to localize because it is embedded in one of those modules. What they did with our tool is they made a change to their RTL and immediately ran SLEC RTL. We gave an equivalence check that said either the design had not changed functionally or we localized the bug quickly to a very specific point where they could quickly make the change. When you are looking at that flow, you are looking at pretty much every designer as well as the verification engineer who needs to signoff on the design being able to use the tool. So there are two different scenarios of use. It is as easy to use as Formality or a Conformal EC type of use model. The designer can run this immediately because he has all the other files he needs. He does not need to write a testbench. He has the two designs and all the info we need from him. It is very similar to what you would give a design engineer to make sure he hasn't broken the design by making these optimizations. This second scenario is for RTL verification engineer who needs now to independently verify this design. He has a tool he can use to leverage the previous verification run where he has already verified the previous RTL by comparing it to a verified design. In typical use you are looking at every design engineer having access to at least one of our licenses and a simulation farm or RTL farm running this tool on each of the blocks that has been modified. It does not eliminate the need for simulation. We do require a golden model to start with. But it helps the subsequent changes and the convergence by being able not to run system level simulation so many times which is very expensive in terms of run time and number of license.

Whom do you see as your competition?
There are some products which are really not competition, but have similar use models. They would be Conformal EC and Formality. They are RTL to gate level equivalence checkers. They are primarily known as combination equivalence checkers because they handle a little bit of sequential differences but they are very limited. These kinds of tools can equivalence check when registers boundaries are more or less fixed and when you have not made a substantial sequential change to the design. That's not the type of change people are making any more. They are making architectural changes to save power. They are making clock gating changes. We are similar to these tools only in the use model. But we do sequential analysis which is substantially different than what these tools do. In some sense you use SLEC at the high end and use Formality and Conformal EC to compare your RTL to gate, then you basically have a complete flow in terms of using formal equivalence checking at the highest and at the gate level. There are probably some areas where you could use both the tools but there is a very small overlap. They are complementary tools.

Calypto is venture backed. How much capital has been invested?
We have four investors. Tallwood Capital, I mention before, is our primary investor. Walden International and Tallwood were our first round investors. We had a second round in September 2004 where we added two more investors: Jafco, who helps a lot with the Japanese market, and Cipio Partners which used to be Infineon and is based in Europe. Between the two rounds we have raised about $22.5 million. They are looking at this as a very long term play enabling the move to ESL, providing fundamental technologies for that.

How many customers does Calypto have? How many licenses?
The ones that we have permission to name are Renesas, FreeScale, Canon, TI and STMicro. The number of seats? We have lots of them. They are all multiple licenses deals. The longest we have done is a three year multi-license, multi-product deal. They are all substantial deals. Again we are focusing on the top twenty semiconductor firms. We do have a few other customers.

How do you sell your products?
We sell direct in North America and Japan. We will be announcing distributors in Europe, Korea and India

How many employees does Calypto have?
We have about 50, predominantly based in Santa Clara. We have a satellite R&D office near Delhi.

You recently hired a new CEO. What expertise did he bring. What was the motivation for the hiring?
I was CEO before that. From my background you can probably guess that I am highly technical. This was a very technical company. We have close to 20 Ph.D.s in this company. We are solving very mathematical problems. We spent the first two to three years focusing on fundamental technology. At that point when we had a few customers, we felt we should take a more customer centric approach because it is a new field, a lot of missionary activity in this area. Methodology is very key. I wanted to focus more on the strategy and direction of our company in terms of our partnerships. We have two very strong partnerships that we have announced, namely Mentor and Forte.

Behavioral Synthesis is a very complementary technology to us. Even though we don't define ESL purely based upon synthesis, a lot of our customers are doing hand design. We needed methodology help. We felt that somebody who has been in the semiconductor field that had gone through their issues and pain would bring that perspective to us and more operational expertise. I can focus much more on technology, the partnerships and so forth. Tom Sandavol has been with us 4 or 5 month. He is bringing that level of expertise. That's the primary reasoning behind that.

Are these partnership arm's length marketing relationships?
No! They are very technical with a lot of cooperation between R&D departments. One of the reasons we have seen a delay so far in the adoption of behavioral synthesis for example SystemC, C++ and SystemVerilog code, is that they have not been quite happy but when people are done with writing RTL by hand and using our tool to do equivalence checking etc, they want to automate that process. They are very interested in behavioral synthesis. In my opinion there are two major issues preventing them from adopting behavioral synthesis besides the maturing process of the quality of RTL coming out of it. One is the verification of the RTL that comes out of Behavioral Synthesis. Behavioral synthesis is an early generation technology. Even if it matures, there needs to be a good verification tool. Unfortunately the testbenches you write at the system level, at the C level, are not applicable to RTL because RTL has completely different timing behavior. The SystemC or C++ may not even have any timing.

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