TSMC's Reference Flow 7.0 and DFM Initiative

Perhaps the biggest beneficiary of TSMC's Reference Flow 7.0 is Magma who was added as a third implementation track. Clearly Magma thinks so. During DAC I attended a “free” dinner hosted by Magma. Prior to the meal Magma and TSMC gave presentations. So much for the “free” dinner. During his presentation Rajeev Madhavan, Magma Chairman and CEO, said
“We worked with TSMC for a long time. Achieving this Reference Flow for Magma is a major, major significant achievement. For the last few years we have had customers talk about that we are not in the TSMZC reference flow and that you are not compliant with TSMC. Even though Magma has a lot of customers, this was a major stumbling clock. .. I really want to thank TSMC for the excellent support they provided us in making this happen.”
TSMC is not the only foundry with reference flows. For example from UMC (United Microelectronics Corporation) website we have:
Given the deep sub-micron design challenges that circuit designers are facing, UMC Reference Design Flows provide customers with silicon-proven design methodologies that reduce time-to-market by enabling manufacturability. The UMC Reference Design Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, leakage power and design for manufacturability and adopt a hierarchical design approach built upon silicon validated process libraries. The UMC Reference Design Flows cover from schematic/RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been correlated to UMC silicon and can be interchanged for added flexibility.
Chartered Semiconductor Manufacturing also has reference flows with Cadence, Synopsys and Magma. ARM has the ARM Implementation Reference Methodology.

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Cadence Reports Q2 Revenue Up 12% Over Q2 2005 Cadence reported second quarter 2006 revenue of $359 million, an increase of 12 percent over the $321 million reported for the same period in 2005. On a GAAP basis, Cadence recognized net income of $30 million, or $0.10 per share on a diluted basis, in the second quarter of 2006, compared to $0.5 million, or $0.00 per share on a diluted basis, in the same period in 2005.

Intel Unveils World's Best Processor; New Product Line Delivers Record Breaking Performance While Consuming Less Power Intel unveiled 10 Intel Core 2 Duo and Intel Core 2 Extreme processors for consumer and business desktop and laptop PCs and workstations. The desktop PC version of the processors also provide up to a 40 percent increase in performance and are more than 40 percent more energy efficient versus Intel's previous best processor. The Intel Core 2 Duo processor family consists of five desktop PC processors tailored for business, home, and enthusiast users, such as high-end gamers, and five mobile PC processors designed to fit the needs of a mobile lifestyle

STARC Adds Magma's Quartz SSTA Statistical Analysis and Optimization Solution to Variation-Aware 65- and 45-nm Design Methodology Magma announced that the Semiconductor Technology Academic Research Center (STARC) of Japan has chosen Magma's Quartz SSTA statistical static timing analysis and optimization software for its process-friendly design flow methodology project for 65- and 45- nm and smaller geometries. Quartz SSTA is part of the variation-aware design methodology that's currently under development and slated for early 2007 release.

Other EDA News

Agere Systems Adopts Sigritys Unified Package Designer for Single and Multi-die Package Design

Intel, AMD, Wind River and Atmel to Showcase Latest Technologies at Global Sources' Embedded Systems, EDA & Test Conferences

MoSys, Inc. Reports Second Quarter 2006 Financial Results

ADVISORY: Synopsys Announces Earnings Release Date and Conference Call Information for the Third Quarter Fiscal Year 2006

Cre8Ventures Houses Start-up, Mirics Semiconductor, at Fleet Offices

Fujitsu Microelectronics Solutions Selects Mentor Graphics Catapult Synthesis Based on Quality of Results in Wireless Communication Applications

Synopsys Extends Liberty Modeling Standard to Enable Variation-Aware Design

Altera Granted Conditional NASDAQ Listing

Ansoft Releases ePhysics v2

Faraday Collaborates With Novas to Accelerate Debugging of Designs Containing Memory IPs

Mentor Graphics Delivers First Hardware/Software Processor Support Package for the ARM Cortex-M3 Processor

Amalfi Semiconductor Turns to Cadence Kit to Speed Up Product Development for Cell Phones

Siemens Expands Its Use of Cadence Incisive Formal Verifier to Improve Time to Market

Other IP & SoC News

ANADIGICS Announces Production Shipments of Dual-Band Power Amplifiers for LG Electronics EV-DO Chocolate Phone

AMCC to Acquire Quake Technologies

TI Introduces Complete Current-Shunt Monitor with Integrated Comparators and Voltage Reference

RF Transmitter from Semtech Offers Low System Cost Implementation for Wireless Security, Home Automation Applications

Atmel Adopts Configurable ARC(TM) Video Subsystem for Multimedia Handheld Devices

EMCORE Corporation, Group4 Labs, and Air Force Research Laboratory Announce World's First GaN-on-Diamond Transistor

MOSAID Brings Motion to Dismiss Micron Complaint

Texas Instruments Releases to Production PCI Express x1 Physical Layer Device

Avago Technologies Announces New Gate Drive Optocouplers in Stretched Small Outline Packages for AC and DC Brushless Motors

Fujitsu and Tokyo Institute of Technology Announce the Development of New Material for 256Mbit FeRAM Using 65-nanometer Technology

Toshiba Develops LBA-NAND(TM) Flash Memory With Logical Block Addressing for Embedded Applications

TI's Receive Signal Chain Demonstration Kit Simplifies Ultrasound Designs

MagnaChip Launches New TFT One Chip Solution for Mobile Phones and MP3 Players

Leadis Technology Announces 262K QQVGA Color STN Driver IC

Tundra Semiconductor Host Bridge for PowerPC(R) Selected for Industry's First PrAMC Module for High-Performance Telecom Applications

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