Forte Design Systems' Forte
Is there a regional aspect to adoption of ESL?
The regional aspect is going down. Plus the companies that are the largest semiconductor companies in the wold are investing. It is also true that Japan and Korea happen to be ahead of the US market. But we have customers in all the markets. We see it coming up to speed pretty evenly now. The US is still behind but it is at least moving where it wasn't moving a few yers ago.
It sounds like a chapter out of “Crossing the Chasm”.
Absolutely! One of the challenges is that engineers by their nature are fickle. When you read Crossing the Chasm one of the things it mentions is that you can only reference either somebody in your space or geography. The best case is both. But if you are a consumer electronics company in the US and you hear that these really smart Japanese guys are up to something, it's just human nature to say to your buddies “Yeah, but that's the Japanese guys. They don't do design like we do design”. That's right out of the Chasm book. It's the same sort of thing. But what has started to happen is that there are companies out there that are worried about other companies. You take the classic example of Intel versus Samsung. Intel is worried about Samsung. They are worried that this is a company that has gotten into the consumer electronics space in the last 5 years and are doing quite well. Sony, Toshiba and other companies are worried about Samsung. Samsung is worried about Philips and others. It is the case that these fellows are in the same ecosystem. They are very concerned about one of their competitors getting an advantage. They recognize that ESL is a way that is significant to them. They are investing in making sure they understand the benefits.
Speaking of investment, the last investment in Forte was 3 years ago.
That's about right!
Any plans to raise additional capital?
We don't have much trouble raising capital. I am actually concerned at this point whether we can use some more. Because we have become more successful it does consume money to do that. It's not out of the question. We might do something this year. But it would not be a big one.
What is Fort's sales model, direct, distributors?
We are direct. We have our own office Forte KK in Japan. We have an office in Europe and of course in the US. We have one distributor that is in Korea.
How many people does Forte employee?
The count is about 50 people.
How many of those are in R&D?
Of the 50, it is close to 30 maybe 35.
Are they all located in one place?
We have three locations in the US. We have the headquarters which is in San Jose. We have a small engineering contingent there plus the administrative staff including me. We have an office up in Redmond, Washington with more engineering. Then we've got a large engineering group in Pittsburg. They basically came out of CMU. It's a very tight team.
What is Forte's revenue?
I can't give specific but we are growing quite nicely at this point.
Would you give me an overview of Forte's product portfolio?
We have essentially one product, Cynthesizer, which is a SystemC to RTL synthesis. We have continued to add features. We just recently announced FPGA support. We announced TLM. There are a bunch of things we have been doing around the main tool but its is essentially one product.
When did you add TLM support?
That was in the last release in January.
What do you see support for TLM doing for Forte?
I think that's going to be very important in the SoC world. TLM is really necessary. We are getting quite a bit of interest from our major customers. We are trying to supply them with some models that will help them with that.
Brett: If you go to our larger vendors, one of the things they are trying to do as they put together their ESL flow, is to incorporate software into the flow. These systems that they are building are quite large, pretty complex. By having the ability to handle TLM what we can do is allow them to abstract the interfaces out between the blocks. So for instance, if you have a big block talking to another block, you do not have to have the pin level interface in your model during the simulation. You have just a TLM interface. That enables you to pass maybe an entire megapixel CCD image from one block to another without having to simulate all the events it would take to get it 100 bytes at a time or whatever their interface looks like. What happens then is they have this high speed verification or simulation model that they can integrate software into or any other aspect of their verification. We can read that model directly and automatically synthesize the interface between the blocks. This comes from a library of predefined and pre-verified interfaces that we have. This allows customers to write these models very easily, simulate it very quickly. Now they don't have to worry about going back and making a mistake when they put their interfaces in.
Forte has announced something in the area of power optimization. How does that work? What is the benefit?
The benefit is pretty clear. You get the ability now to trade off area versus power versus performance. Where typically as a RTL designer what you do is write something for a certain performance level. You can figure out that for this to happen the area becomes a consequence. If I want this to happen in 8 clocks, my area will be X. If I want to make it 10 clocks, I could probably shrink the area a little bit. If I want to make it 4 clocks, I could up the area a little bit. What they always did afterwards was then go off and measure how it affected power. There were some techniques and tricks you could do along the way to say I know if we implement the code like this my power utilization will be better overall although I don't know what it will be. I just know that is better. What we have given the customer is the ability to turn on a set of power optimizations. It will generate another hardware implementation for you. You can quickly see then how this hardware implementation would affect you. The difference between using something like Cynthesizer and RTL code is that we can generate 100 of these RTL implementations in a matter of literally hours. You just change the constraints of the synthesis tool. You can get different areas, different latencies and different power constraints. You can now go off and plot a graph that shows here is my best area, here is my best power and here is my best latency. And here is the point on the curve that gives me optimal values for all three of them. It really gives you this ability to use design exploration which is simply not possible in an RTL flow.
What is the pricing and packaging of Cynthesizer?
It is pretty straightforward. We sell a one year time based license for $250K. We are really in the business of making sure the project the customer is working on is successful. We work with our customers to make sure that they have not only the tools because that is an important part but we also have a full methodology and training for that methodology. We can go in and get customers who may not understand how a SystemC flow is going to integrate with their existing flow directly and provide them with a methodology and methodology services that are really the lynchpin to make this whole solution successful. Much beyond the tools.
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