Silicon Canvas Introduces a New Laker Product

A New DDLtm Approach boosts the productivity of Analog/Mixed-Signal designs by 10X while maintaining handcrafted layout quality

San Jose, Calif., July 21, 2006 - Silicon Canvas, Inc. today introduced a new Laker product, which will boost analog/mixed-signal design productivity by10x while still maintaining handcrafted layout quality. Overall operational efficiency can be greatly improved for all cost sensitive analog/mixed-signal design houses. Highlights of this new release include an intelligent schematic generator, auto static and dynamic constraint extractors, optional manual constraint editor, and transistor level custom placer and shape-based custom router.

With Analog Designs outpacing Semi market (EETIMES June 23, 2006), and with greater interest and desire to shift from a traditional polygon pushing methodology to more efficient methodologies, the new release is very attractive to a broad range of existing customers and new prospects. Laker DDL automatically extracts constraints from design netlist, simulation results and design properties. Based on these constraints, the layout is automatically generated through a built in constraint driven place and route engine. Since the constraints are directly extracted from the design, the chance of inconsistency through manual effort is greatly reduced.

The methodology for the analog design is considered to be primitive and hasn't seen too dramatic a change in the past. Compared to the progress of its digital counterpart, polygon pushing remains the mainstream layout methodology. However as the product life cycles get shorter and time to market pressures mount, designers are searching for a more productive methodology. The conventional SDL (Schematic Driven Layout) is able to achieve a certain degree of success within a very limited scope. A constraint-driven layout methodology was later introduced with intentions of taking analog specific needs into consideration. A tremendous resistance was encountered because of the labor intensive constraint preparation process and the dramatic layout quality degradation as shown on Fig. 1.


Laker's customers have enjoyed an enormous productivity gain through the Laker SDL flow. Now with the introduction of Laker DDL features and methodology, the customer can expect a10x productivity gain. As shown in Fig. 2, Laker DDL includes a transistor level schematic generator, a static constraint extractor which can analyze the design netlist and automatically extract the device matching and symmetric constraints for analog circuit; a dynamic constraint extractor which can automatically extract constraints like current density, operating frequency and voltage drop etc. based on the simulation results. These capabilities can dramatically reduce the tedious, error prone process of constraint generation, ensure constraint consistency and reduce the preparation efforts.


After the automated constraints extraction, designers can use the constraints editor to modify or add new constraints, such as differential pair, shielding and equal routing length, etc. All constraints will be stored in a unified database that is shared by both design and layout. After the designer's review, the system will pass these constraints to Laker's transistor level custom placement engine, which will place the devices based on the design signal flow and/or schematic topology together with matching and symmetry constraints. Laker's built-in shape-based custom router can be called upon to complete the wiring.

"The introduction of Laker DDL methodology is what we have been waiting for. The consistent constraints from design to layout save a lot of communication time between designer and layout engineer. Also the analog layout centric flow can generate handcrafted layout quality in a very short time. I especially like the matching creator with matching route since it can generate matched devices without iterations.", said Sean Lin, President of Silicon Topology, which is one of the biggest analog layout service companies in Taiwan.

"Laker DDL eliminates the time consuming and error prone process of constraint preparation in the conventional constraint-driven flow", said Dr. Hau-Yung Chen, president of Silicon Canvas, "moreover, the unified schematic and layout DB together with our patented Magic cell device model and the flexible hierarchical manipulation capabilities delivers near hand-crafted layout quality".

Laker DDL is available immediately for Sun Solaris (32-bit and 64-bit), Linux (32-bit and AMD 64-bit), and HP (32-bit and 64-bit) platforms. U.S. pricing for the tool begins at $70,000 for a one-year time-based license.

Rating:


Review Article Be the first to review this article

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy