Special DAC Session on MPSoC Design Tools Includes Talks by Imperas, Tensilica Representatives; Special Session Intended to Focus on Emerging Challenges Related to MPSoC Design

PALO ALTO, Calif. & SANTA CLARA, Calif.—(BUSINESS WIRE)—July 18, 2006— Representatives of Imperas Inc. and Tensilica,(R) Inc. will participate in a special session titled, "Multi-Processor System-on-Chip (MPSoC) Design Tools," during the 43rd Design Automation Conference (DAC) Wednesday, July 26, from 8:30-10 a.m. at San Francisco's Moscone Center.

Session 16, to be held in Room 306-308, will describe problems associated with the design and verification of SoCs that use multiple processors. It will cover system-level modeling and application partitioning and mapping as it pertains to challenges faced by MPSoC designers. Presenters will show how software design tools can help alleviate some of these problems, what parts of the design flow can be fully automated, and what parts can be assisted by design tools.

Speakers include Grant E. Martin, Tensilica's chief scientist, who will present a paper titled, "Overview of the MPSoC Design Challenge." Peter Flake, chief scientist of Imperas, will describe "System-Level Automation Tools for MPSoC Designs." Professor Ahmed A. Jerraya of TIMA/CNRS will offer a look at "Programming Models and Hardware/Software Interface Abstraction for MPSoC." Pierre Paulin of STMicroelctronics is the session chair.

Imperas will hold select meetings with MPSoC designers and users during DAC in Booth #336. To schedule a meeting, contact Frank Schirrmeister, Imperas' vice president of marketing, at (408) 983-1260 or via email at franks@imperas.com.

About Tensilica

Tensilica, in Booth #3548 at DAC, offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard series cores and with full designer configurability with the Xtensa processor family. Tensilica's low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

About Imperas

Imperas (pronounced 'imp-ear-as') is a new software company producing groundbreaking products in the unified System Design Automation space. By blending hardware and software technologies and design processes together, Imperas provides methodologies, technologies and products to enable efficient design and programming of Multiprocessor Systems on Chip (MPSoCs). Funded by Accel Partners and Pond Ventures, Imperas has a U.S. headquarters in Palo Alto, Calif., and an engineering office in the U.K. Corporate Headquarters is located at: 2200 Geng Road, Palo Alto, Calif. 94303. Telephone: (650) 575 8391. Facsimile: (650) 887 0319. Email: information@imperas.com. Website address: http://www.imperas.com

Imperas and Tensilica acknowledge trademarks or registered trademarks of other organizations for their respective products and services.



Contact:
Corp. Comm for Tensilica
Paula Jones, 408-327-7343

Email Contact
or
Public Relations for Tensilica
Erika Powelson, 831-424-1811

Email Contact
or
Public Relations for Imperas, Inc.
Nanette Collins, 617-437-1822

Email Contact



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