Book Signing - On Monday, June 24th, at 4:15 PM, Lee Wood of MP Associates is hosting a "mass" book signing in the DAC Pavilion on the Exhibit Hall floor. I suspect there will be many authors present, but the book that I hope will be there is The Electronic Design Automation for Integrated Circuits Handbook. This massive, 2-volume work edited by Louis Scheffer, Luciano Lavagno, and Grant Martin is a rich resource for anyone who really wants to delve into the details of what makes the EDA industry tick. The list of luminaries that have composed the 45+ chapters in the set reads like the proverbial Who's Who of EDA. I'm not going to list any names, because they should all be listed, but suffice it to say - Grant Martin sent me a copy of this boxed set and I have spent a number of hours turning pages and enjoying the technical depth and breadth it offers, and marveling at the list of contributors. The text is extremely well written, and each chapter includes a lengthy list of references - the chapter on Logic Synthesis alone includes 249 papers and sources. I'm not suggesting that everything you ever needed to know about EDA is in this boxed set, but if you want a launch point to begin a thorough study of a topic, or a topic within a topic, related to electronic design automation, I don't think, today, you could find a better place to start!
Cable Cars - At 5 bucks per ride, they're way too expensive. But if you've never ridden one What, you can't part with 5 bucks? Just do it! You won't find any locals on board, but who cares?
Castro Theater - Lovingly restored, complete with organ that rises up from below, and an eclectic set of films most days of the year it's part of the San Francisco scene.
CEDA Distinguished Speaker Reception - The lecture by Mentor's Janusz Rajski and reception will be on Monday, July 24th, from 5:30 PM to 7:30 PM in Room 124 at Moscone Center. This event is part of a series sponsored by CEDA to honor the best papers at DAC, ICCAD, and TCAD. Rajski et al's paper was the TCAD 2006 Donald O. Pederson Best Paper, co-authored with J. Tyszer, M. Kassab, and N. Mukherjee, and titled, "Embedded Deterministic Test."
City Hall, Opera House, Davies Symphony complex - All Blue & Gold, the City Hall is a benediction to the other two structures. The whole thing is best enjoyed from the second floor lobby of Davies Hall. Go and you'll see why.
Cliff House - It used to be beautiful, several iterations ago. Now it's just a hunk of cement. But the view is most spectacular. If you're a tourist, you'll love the food. Otherwise, eat elsewhere.
Coit Tower - Don't even ask why you need to go. Just go. The view? Yes! The WPA murals in the lobby of the building? Historic and terribly moving.
Convergence at DAC - According to a spokesperson at STMicroelectronics, Alessandro Cremonesi's keynote address, on DAC Thursday will help attendees answer the question of whether convergence is a technical reality or a business strategy. Cremonesi is ST's Strategy and System Technology Group Vice President and Advance System Technology General Manager, and he is promising to highlight a number of existing and possible future applications in his talk, to identify various challenges in designing convergence applications for today and tomorrow, and to discuss the business opportunities - and threats - that both entrepreneurs and entrenched players should be aware of. He will also testify to the fact that the design community, with substantial help from its friends in EDA, has made lots of progress merging, and converging, technologies to improve contemporary life - but there's still lots of work to be done, on both the technical and business sides. The intention of Cremonesi's keynote address is to let attendees know what they can do to contribute to those efforts. The event takes place in the Gateway Ballroom at 12:45 PM on Thursday, July 27th. Be there!
Darren Tay, CEO at Nanno SOLUTIONS - Nanno SOLUTIONS' technology makes use of a fab's actual process variation data and transforms it into realistic values, which enable designers to improve design performance, including parametric yield. The first products, Nanno-WiN and Nanno-CaL provide realistic, statistically based, worst-case interconnect models for RC-delay, crosstalk and IR-drop. Nanno SOLUTIONS' models can be used for front-end, as well as back-end design during the pre-layout stage. They are built using actual process data from the fabs to improve accuracy, run-time, accelerate yield prediction and reduce design skew.
Dennis Brophy, Mentor Graphics - The must-see, must-attend verification lunch on Tuesday is with "the" MythBusters as Mentor details its AVM 2.0 Cookbook.. First-come, first-serve seats are available, but going real fast! Added bonus: the first fifty to visit the Denali booth after lunch, get Denali party tickets for that night. It's all happening Tuesday, July 25th, from 12:00 Noon to 1:30 PM in Room 102 at Moscone Center. With all these vendors at DAC telling you that their products are the best, how can you know what's true and what's hype? This sounds like a job for MythBusters! Come and meet the MythBusters from the Discovery Channel TV series. Special effects experts Adam Savage and Jamie Hyneman will show you how they use modern-day science to show you what's real and what's fiction by taking you inside the world of MythBusters. They will share their methodology for analyzing a myth and planning and constructing experiments to determine whether the myth is plausible, confirmed, or busted. The one thing they can't always do is correctly predict the outcome of their experiments. Sometimes, the bigger the myth the more spectacularly the experiment fails...or succeeds. Of course, when designing a chip, failure is not an option. At Mentor, we've created the Advanced Verification Methodology (AVM) to help verify the most complex designs. In the spirit of the MythBusters, whether you're a verification novice, or an expert like Adam and Jamie, you'll be able to use the AVM, building on the library Mentor provides, and reusing components across teams and across projects, to assemble the verification environment you need to confirm that your chip will achieve first-pass success.