Standards - IP Arena


Mentor Graphics Announces New Bit-Accurate C++ Datatypes that Accelerate Algorithm Validation by 10x Mentor announced the availability of Algorithmic C(TM) datatypes, new high-speed datatypes based on ANSI C++. These arbitrary-bit-width datatypes enable algorithm, system and hardware designers to precisely model bit-true behavior in C++ specifications while accelerating simulation speeds by 10-200x. Mentor Graphicsis making the new C++ datatypes immediately available to the electronics designers and (EDA tool vendors free of charge on its website.

Pyxis Technology Raises $9.2M in New Funding Pyxis Technology announced that it has raised $9.2 million in Series B funding. Formative Ventures of Menlo Park, California led the round with participation from Series A investors: Austin Ventures and CMEA Ventures. Funds will be used for continuing R&D and to begin developing sales and marketing infrastructure to support customers. The company is focused on DFM routing technology based on a new software architecture optimized for design for manufacturability, which reduces design closure cycle time while improving overall design yield.

ADVISORY/ Five Reasons to Stay at DAC 2006 until the End of Thursday, July 27th At 4:30pm on Thursday there will be a panel “DFM: Where's the Proof of Value?". Panelists from Aprio Technologies, Blaze DFM, Clear Shape Technologies, Mentor Graphics, Pyxis Technologies and Synopsys will present information on how their DFM tools fit into a fixed design methodology, budget and timeline, and give real-world examples of expected ROI.

Micronas Tapes out HDTV Chip With Synopsys' IC Compiler This new chip is a key part of Micronas' drive to improve picture and sound quality for flat-panel TV and to provide benefits to manufacturers in the total cost structure from R&D to production, based on very high integration. Using the Galaxy design platform with new IC Compiler optimization technology, Micronas was able to tape out this design at the required performance while achieving a remarkably high utilization in excess of 90 percent.

Sequence Powers Up For DAC -- Booth 1614; New PowerTheater 65 Highlights Low-Power Leader's Strategy For 65nm Design Sequence Design will unveil a host of new technologies for low-power design at this year's DAC, headed by its new Silicon Aware PowerTheater 65, an RTL power analysis and management solution targeted to address the challenge of designing at 65nm and below.

Synopsys Continues IC Compiler Momentum With 2006.06 Release The 2006.06 release of IC Compiler, Synopsys' next-generation place-and-route system, delivers advances in the areas of integrated design planning, enhanced physical test, advanced low-power design, true concurrent multi-corner/multi-mode optimization, and design-for-yield techniques. The 2006.06 release allows flat floorplan creation and refinement in the same environment as physical implementation -- placement, clock tree, and routing. These capabilities utilize proven technologies from the JupiterXT tool for floorplanning, automatic high-quality macro placement, and automatic power-network synthesis and analysis. The integration brings about commonality in graphical user-interface, timing analysis, placement, and global routing technologies, to drive higher-quality floorplanning and faster time to results.



Other EDA News

VaST Systems Technology Names Colin Lythall as Director of Engineering

Cadence Test and Formal Verification Technology Speed Time to Market for Matrox

VeriSilicon Announces Acquisition of ZSP Digital Signal Processor Unit from LSI

Azuro Enables PowerCentric for 65nm

GiDEL's PROCWizard™ enables full hardware and software integration.

43rd Design Automation Conference to Feature 44 New Exhibitors

Ross Video Selects Synopsys' VCS SystemVerilog Native Testbench to Increase Verification Productivity and Predictability

Altera Adds New Member to Cyclone II FPGA Family

Accent Emphasizes Greater Design Chain Productivity with Semiconductor Data Management Solution from ENOVIA MatrixOne

Optimal Corporation, Rio Design Automation Partner to Solve Chip-Package Co-Design Challenge

Nanno SOLUTIONS Launches Company

DAFCA Announces Availability of ClearBlue(TM) Debug Infrastructure IP and Software Product Family

Real Intent Introduces Conquest(TM) and Ascent(TM), Leading the New EnVision(TM) High-Performance Formal Verification Family



Other IP & SoC News

Rambus and Matsushita Sign Patent License Agreement

STMicroelectronics' New Voltage Regulator Shrinks Portable and Battery-Powered Devices

ISSI Acquires Alliance Semi Synchronous SRAM Product Line

SigmaTel Announces Second Quarter 2006 Earnings Conference Call and Webcast

MagnaChip Introduces CMOS Sensor CSP Solutions

UMC Collaborates with NTU to Deliver RF Chip for WiMax

Abilis Systems Announces Manufacturing Agreement With IBM Microelectronics




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