The Business of DFM
Nitin Deo, Ponte Solutions -- Yes, but that is expected. I think it will take at least a year before engineers start using these tools as part of their job and then the information trickles down to VCs. We got the first indication of that just two weeks ago when a potential customer called us on his own and now we are in the process of setting up the complete flow for his design team.
Riko Radojcic, Qualcomm -- There is no doubt that DFM is still in a 'missionary sell' phase of adoption. The big barrier last year was access to the appropriate process data necessary to make the DFM simulators work. That barrier has been overcome, as per the recent announcements from all major foundries. However, there are still significant barriers to be overcome before DFM, under its current definition, becomes mainstream technology. The barriers are now more on the user side, and the principle challenges are associated with integration into the design flows. In addition, the value proposition from these tools is still anecdotal and qualitative, making conventional ROI analysis hard to do.
Rob Aitken, ARM -- I would describe it as a learning phase, and I think we are beginning to emerge from it. For example, designing layout that is robust in the presence of lithography variation requires some understanding of the manufacturing process. The first tools in this space required explicit, detailed descriptions of every aspect of a process recipe, and understandably foundries were generally unwilling to provide these. Instead, they offered DFM recommendations in the DRC decks, which helped yield, but at the expense of over-constrained design.
ARM spent the last couple of years working with the foundries to develop metrics and methods that identified lithographically important issues in a more efficient manner than a DFM deck, but without requiring detailed process information. This resulted in high quality physical IP at 90 nanometers and 65 nanometers. The upcoming generation of lithography simulation tools is now using encrypted process data and going forward will enable even better interaction between design and manufacturing without compromising the secrets of either.
Srinivas Raghvendra, Synopsys -- Designers who are at the 65-nanometer node are asking for DFM solutions, so it's clear that we are no longer in the evangelism mode.
Thomas Blaesi, SIGMA-C -- Yes, to some extent, because of its complexity.
Won-Young Jung, Nanno SOLUTIONS -- Yes!
Yervant Zorian, Virage Logic -- I think you are asking if I had some money to invest in a DFM company, or to buy a DFM solution, what would I do? How would I choose the best among many? First, I need to find out which DFM product, and thus which company, results in the highest yield. DFM solutions today definitely differ from each other. Some solutions have minor yield improvements versus others, such as Virage's silicon-aware IP, which provide total self-repair that often increases the yield as much as 200 percent. So, I would put my money where I see the greatest increase in yield. Whether to buy or invest, is something I would have to examine on a case-by-case basis.
6) If you had $10 million tomorrow from an investor, how would you spend it enhancing your DFM offerings, or what additional tools would you buy from your DFM vendor, if you're a user?
Jacob Jacobsson, Blaze DFM -- Because of the importance of leakage power and variability, we believe that our product offers substantial benefits to the vast majority of engineers designing chips with sub-100 nanometer process technologies. Given that, the best use of the money would be to expand our sales, distribution, and support networks to get our products into their hands as quickly as possible.
Atul Sharan, Clear Shape -- If Clear Shape got an extra $10M, we would expand our R & D and Applications to better penetrate and serve customers.
Dale Pollek, ChipMD -- Deployment or call it “Channel.” With the hundreds of silicon-proven design successes of DesignMD now, and hundreds of users on all three major continents of EDA users (Europe, Asia and U.S.), the only limit to our growth will be adding enough pre-sales support, sales and marketing staff. We are growing now based on profits of our sales successes, so extra cash invested would be able to return on itself very quickly. For us, it is now a safe-bet opportunity for investors.
David Thon, Cadence Design Systems -- We'd continue to invest in developing manufacturing models that are crucial to a manufacturing-aware design flow.
Dwayne Burek, Magma Design Automation - Probably one of the biggest limits to more wide-spread adoption is being able to provide IDM or foundry-specific solutions. So, this is not necessarily a lack of technology, but more of a resource bandwidth situation -- investing in additional resources to come up with a more scalable infrastructure for foundries and IDM's to pass manufacturing-related data and models to the implementation and verification tools, and for implementation tools to pass more design intent to manufacturing is where we need help.
Mike Gianfagna, Aprio Technologies -- I would hire a lot more AEs and QA staff. These two job descriptions, more than any other, enhance the customer experience.
Naeem Zafar, Pyxis Technology -- We just got our $10M last week, so we are planning the answer to this question even as we speak. But, tighter interconnection between the DFM analysis tools and design implementation tools is the future (just like timing and routing were in 2000 and 2001).
Nitin Deo, Ponte Solutions -- If we had $10 million, we would build a solid platform to address all yield-related issues (i.e., random defects, systematic defects, lithography issues) for all design styles (libraries, memories, full chips, etc.). This platform should be able to adapt our own models, as well as anyone else's models for such process phenomena. Today, all DFM suppliers are addressing only one or two aspects of the whole yield issue. That's not going to work for too long.
Rob Aitken, ARM -- Now that the conventional lithography-centric DFM/DFY space is reasonably well covered by commercial tools, the next DFx challenge is design for variability. Example applications include statistical timing, design centering, and circuit tuning. These approaches take manufacturability as a starting point, which means a variability window in practice, and then look at optimizing the design to either use the variability to benefit performance or power, or quantifying the variability in order to locate a design point that minimizes its effects.
Thomas Blaesi, SIGMA-C -- Unlike the electrical side, where SPICE is the standard model to describe the transistor, currently, there is no standard process model that can be utilized by a series of tools in a DFM flow. Creating this would put the money to good use.
7) Are the in-house DFM tools really the majority of those being used today ... i.e., is there really a market in the EDA space for vendors other than the big 3 or 4 who have the channel and the R&D budgets to pursue expensive advancements in this highly technical area?
Jacob Jacobsson, Blaze DFM -- As we mentioned before, there is a lot of useful manufacturing information in a standard design kit that is going to waste on the design side. There is a lot of useful design information that is not being put to good use on the manufacturing side. There are a lot of obvious things that should be done that aren't being done. But, it takes a good understanding of both design and manufacturing to be able to recognize these things. That's been one of the problems. Chip designers don't recognize useful manufacturing information and manufacturing engineers don't recognize useful design information. Electrical DFM solutions are infused with knowledge of both worlds and recognize how to transfer that information from each side to the other in a way that is useful to both.
Atul Sharan, Clear Shape -- We do not run into any in-house DFM tools. Almost all innovation in the last 10+ years has come from start-ups. ALL of Synopsys and Mentor's OPC/RET and DFM offerings have their basis in acquired technology.