The Business of DFM
To be successful, the benefits in terms of yield improvement need to be measurable otherwise the extra revenue generation can only be associated with faster turn-around-time or easier to use tools and flows. So, standalone vendors selling "DFM signoff" or "DFM optimization" tools have a big challenge ahead of them.
Joe Sawicki, Mentor Graphics -- Although John Cooley says my predictions for growth in the DFM market are wrong, there is “real stuff” in this market and real buzz around what's happening in the start-ups. All types of DFM tools - design focused, manufacturing for design, and “old school” tools like DRC, parasitic extraction, and physical analysis - were generating over $500 million by 2004. I believe that market will surpass $1 billion by 2008, and $1.5 billion by 2010. Over 80 percent of today's market is owned by Mentor, Synopsys, and Cadence, while Mentor has a 40-percent market share in the market we serve [which excludes TCAD and yield ramp]. [Comments paraphrased from my phone call with Joe Sawicki.]
Mike Gianfagna, Aprio Technologies -- Not yet. There is a difference between the evaluation phase and production phase. For the most part we're still in the eval or testing phase. Full-production deployment will tell the real story, and that's ahead of us.
Naeem Zafar, Pyxis Technology -- Absolutely! In our case, the value proposition is clear and has economic value. And, we see our partners making money already
Nitin Deo, Ponte Solutions -- Yes, at least Ponte is. We are providing real value that open designers' eyes to previously unknown problems and they can do something about those problems with trade-off between yield and area or yield and timing.
Srinivas Raghvendra, Synopsys -- We can't speak for the other DFM vendors, but Synopsys has a very healthy and growing DFM business.
Thomas Blaesi, SIGMA-C -- SIGMA-C absolutely sees DFM as a viable moneymaker for this industry. It's a major requirement at 65-nanometer nodes, and essential below that. There are point-solutions making money, but the main challenge is creating integrated DFM solutions throughout the design flow.
Won-Young Jung, Nanno SOLUTIONS -- Yes, it has.
Yervant Zorian, Virage Logic -- We are seeing more and more interest in DFM, particularly with the move during the last 18 months from 90 nanometers to 65 and 45 nanometers, and as the impact of random and systematic defects in silicon is increasing. That is why we feel it is more and more important to put the DFM right into the IP. Defect density is increasing, as well, and the need for DFM increases with it. Today's chips at 65 nanometers are being manufactured at a much higher volume, because most of them are targeting consumer electronics -- cell phones, games, and so on. For these high-volume chips, DFM and thus higher yields are very critical. If some company revenue relates to DFM and yield, then these large volumes on the 65 and 45 nanometers will definitely increase such revenue.
3) If OPC/RET and wire spreading have been around for a while, what is the 'new' part of DFM that seems to be generating so much interest?
Jacob Jacobsson, Blaze DFM -- At Blaze, we believe that “Electrical DFM” is the next wellspring of growth, not just for DFM, but for all of EDA. Today, there is so much valuable information, on both sides, that is not being put to good use. There is a lot of manufacturing information that is available in standard design kits that is going to waste on the design side, and there is a wealth of power and timing information that is not being put to good use on the manufacturing side. Since electrical DFM solutions are fully aware of the power and timing requirements of the design, they optimize the design based on manufacturing information and then optimize manufacturing based on design requirements.
Atul Sharan, Clear Shape -- OPC/RET are lithography post-GDS-II solutions, meaning they occur too late to help the designer during design. Wire spreading addresses random manufacturing variations--opens and shorts caused by random particles on the mask. However, at sub-100 nanometers, the biggest DFM issue is systematic variation -- highly predictable variations in shape caused, in great part, by the fact that the lithography wavelengths are now far bigger than the process geometries.
Chenmin Hu, Anchor Semiconductor -- The IC manufacturing process is actually a pattern-transfer process from layout design to mask, wafer, etc. In advanced nanometer technologies, the final patterns on the wafer are very different compared with the original layout designs. Most yield problems, including performance related yield problems, come from pattern transfer. Clear understanding of properties or characteristics of patterns can be a very important 'new' part of DFM.
Dale Pollek, ChipMD -- Peggy, “where's the D” here? I sound like that ancient Wendy's commercial of “where's the beef,” but please help the world understand how anything done at and after layout is considered D, unless the D in DFM is for “Drafting?” Sure, some of the characteristics of the drafting, tooling and manufacturing stages require designers to input and assess the impacts to help make decisions, but that is definitely more “dealing with manufacturability” and not “designing for manufacturing.” Isn't it?
David Thon, Cadence Design Systems -- It's becoming more important that manufacturing effects are modeled within the design flow as design is being done -- rather than remedied in post-processing operations -- so the design will be manufacturable with reasonable yield when it gets to the fab. These manufacturing effects include lithography, CMP, etch, thermal, and others.
Dwayne Burek, Magma Design Automation - There are two answers: a) adding lithography (OPC/RET) awareness into the complete design flow, including P&R, analysis, and DRC. This is important for 65 nanometers, necessary for 45 nanometers; b) TSMC and other foundries are now making DFM information available to their customers.
Mike Gianfagna, Aprio Technologies -- These two applications are parts of a comprehensive solution. You need more applications than just these two, and you need a lot of good integration work to make a real solution. Those pieces form the "new" part.
Naeem Zafar, Pyxis Technology -- That was so 5 years ago! It was the 1st-generation of DFM tools that merely helped fab and mask people -- designers did not even feel it (like a 4.1 earthquake). Then came the 2nd-generation tools, (in 2005 and 2006) where some post-layout changes were done based on DFM analysis. There are examples [in this generation of tools] from Cadence's Catena, Sagantec's DFM-Fix, etc. There was also buzz, as various DFM companies brought out DFM analysis tools for various types of yield problems. Now, in the future, you will see the 3rd-generation DFM tools that promote correct-for-manufacturing designs (both in libraries and wires -- as in routing).
Nitin Deo, Ponte Solutions -- Quantification of those issues. It's like this -- people have known for years that sugar and caffeine are bad for health, but now technology can exactly quantify it for you and also tell you individually what is bad for you given your own health. Similarly, now these technologies are becoming very design-specific -- which is absolutely critical for steady and high yield.
Riko Radojcic, Qualcomm -- The 'new' bit vis-à-vis RET is that there are now tools aimed at designers to help make layouts more RET-friendly. The 'new' bit vis-à-vis wire spreading is that there are now tools that can simulate and quantify the yield benefit of wire spreading.
Rob Aitken, ARM -- Historically, DFM has been considered a post-tapeout activity. OPC/RET has been used for a long time, but it is being used on more layers with each process generation. The current wave of interest in DFM began with the realization that making the pre-tapeout design more OPC friendly would result in a better optimization between performance, area, and yield. However, it's one thing to say that DFM should be more a part of design, and quite another to figure out exactly how that happens. DFM can potentially interact everywhere from library creation through synthesis, place and route, extraction, DRC, and DFT. The challenge has been determining the best place for DFM, from both a technical and business perspective. Many approaches have been proposed, but only some of them will succeed.