Verification Update

Are there any other barriers to adoption out there?
The way people deal with adoption is that they do it incrementally. They say we have all this legacy and we will maintain our current legacy for the products we have. We will launch new products on SystemVerilog. Every medium to large customer we have that has made a commitment to SystemVerilog has taken an incremental approach to it. We've eased the problem for them quite a bit because when you use Questa you do not have to “get rid of” existing methodology. Questa will very happily execute e. If you are an e user, whatever e testbench you have, you have. You can make changes to that testbench with SystemVerilog and quite happily get on with your life. The trick in adoption is to make progress incrementally. Some people want to make faster progress. Some firms will offer conversion services to these people. People take various approaches to this whole thing. The adoption curve is limited by how quickly people can move.

What other hurdles are out there?
Those are the biggest ones. The ecosystem - the Vanguard Program - is a way of having the industry educate itself around the good things in SystemVerilog. Models are needed. IP needs to come out in ways that are compatible with SystemVerilog. Fortunately, the SystemVerilog spec says you must be able to execute plain old Verilog. So, all the old Verilog models will continue to work under SystemVerilog which is a big plus. You can create new models with some of the more advanced features of SystemVerilog.

How would you characterize the adoption of SystemVerilog itself?
Pretty good! As I said 30% of our deals in the first quarter after we released Questa had SystemVerilog in them. The SystemVerilog sales in terms of revenue is significant. The adoption has been rapid. It is more rapid in startups. However, the momentum is picking up in larger companies. We will be able to announce a major deal this quarter with a company that has made a whole sale conversion to SystemVerilog. You are going to see this move to SystemVerilog accelerating.

What about this transition outside of Mentor's customer base?
Aart de Geus recently stood up at an analysts meeting announcing that Synopsys has a reasonably mature SystemVerilog simulator available. I think Synopsys is also experiencing people getting on the SystemVerilog bandwagon. Cadence is a little late but I think that they will catch up pretty rapidly. The other way to judge SystemVerilog adoption is to have a look at how many companies at DAC have SystemVerilog in any of their documentation. Last year at DAC there was a sponsored lunch with an opportunity for companies to stand up and give a 2 minute pitch on what they are doing with SystemVerilog. Over 85 companies got up and talked.

It is there in the industry. Things are moving forward. It is hard to measure precisely. From our own metric we are pleased with what we see. I think Synopsys is experiencing the same. Cadence, I just do not know.

Faster simulators and advanced methodologies. What about front end tools, ESL?
One of the design goals of AVM was to allow people, encourage people, to check things as early in the design as possible. The feedback from our customers is that our testbench and verification approach has to have this abstraction adaptation layer in it because people want to start off with high level models, check throughput and latency at the high level before they spend man years writing RTL only to find that they have correctly implemented the wrong spec. That's what you are trying to prevent. The way to do that is to have a methodology that lets you smoothly shift between abstraction layers so that you can write a very high level testbench to test your high level models and then as you refine your design and add more timing details to it that testbench continues to give you value. In the past the problem has been that you wrote a testbench for a high level model, threw it away and then had to write a new testbench for a low level model. The question always was “Did the two testbenches cover the same functionality?” It may be that when you rewrote your testbench for the lower level, you forgot some key things that you are now not checking for any more. Your design may come out leaning slightly to the right or left.

A good methodology has to span system level down to gate level. The only way to do that is to have those abstraction conversion layers inside your testbench. It is an architecture of testbenches. It is a way of writing a testbench that lets you do that. You can do that with SystemC. You don't strictly need SystemVerilog to do it. It just turns out with SystemVerilog you have a whole lot of help with coverage statement and stuff like that. AVM has really taken that into account because it is one of the key points about becoming more effective.

Product Availability and Pricing?

The Questa 6.2 verification platform ships in Q2 2006 and includes access to the Advanced Verification Methodology portal. Pricing starts at $28,000 USD. The AVM will be available in Q2 2006 at no charge under a standard, open-source license.

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