Initially, Dr. Ranjan served as director of engineering, heading development of Jasper's industry-leading full formal solution, JasperGold(R) Verification System. He assumed the role of Chief Architect in 2005 and pioneered several next-generation product features. Now, in his new role as CTO, Dr. Ranjan will work closely with key customers, Jasper's R&D team, as well as a number of verification industry luminaries to research new formal application spaces that target correctness where it matters most.
"In his engineering and chief architect roles, Rajeev made many outstanding contributions to Jasper, particularly in increasing formal capacity while simultaneously helping to make the Jasper solution the most user-friendly on the market," said Kathryn Kranen, president and CEO of Jasper. "Rajeev's depth of formal experience, understanding of the customers' design challenges and product development insights will help to further Jasper's technology leadership. Further simplification of the user experience along with powerful product enhancements will deliver significant value to designers and verification engineers worldwide."
"With the growth in today's chip complexity and the increasing demand for higher quality products, formal is rapidly becoming an imperative," said Rajeev Ranjan. "I'm very excited about stepping into this new role and driving Jasper's technology vision as I want to empower design and verification teams with new ways to achieve fast, complete verification with push-button simplicity. Just imagine what designers could do if given a highly intuitive way to leverage formal. And think about what greater automation and increased design visibility would mean to the advanced formal user. The completeness of advanced formal, combined with simulation coverage - this is the future."
Before joining Jasper Design Automation, Rajeev Ranjan was CTO and VP of Engineering at Real Intent, where he led the development of their products and set the company's technical direction. Before joining Real Intent, he was in the Advanced Technology Group at Synopsys, where he co-developed the prototype for Magellan, Synopsys's formal-assisted simulation product.
Rajeev has been active in the area of formal verification for over 13 years. He has served on the program committees of many international conferences including DAC, ICCAD, FMCAD, and CHARME. He has published numerous articles and holds 5 patents in the area of functional verification.
Rajeev received his bachelor's degree from the Indian Institute of Technology, Kanpur, his Masters degree from University of Illinois at Urbana-Champaign, and his doctorate degree in formal verification from University of California at Berkeley.
About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company's flagship product, JasperGold(TM) Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.
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