The Power Forward Initiative will link design, verification and implementation to reduce risk and increase predictability in chip power reduction. Members will work to adopt a new automated design infrastructure aimed at reducing chip power consumption. To achieve its goal, the Power Forward Initiative charter calls for, among other things, the refinement and promotion of a new open specification that captures essential design intent for power and links the design, implementation and verification domains. The group aims to begin the industry open standardization process starting in 2007.
"Cadence believes the greatest gains in developing low-power technology can be made at the architectural level, and we've already been investing in technologies that enable IP re-use and portability," said Mike Fister, president and CEO of Cadence. "By uniting industry leaders, the Power Forward Initiative will steer the industry toward a broader, more systematic, and much more integrated approach to low-power design, providing a platform to enable higher-level exploration while leveraging the good building-block work we've all already done."
"As microprocessor designs shrink and advance, power consumption is top of mind in any new design," said Marty Seyer, senior vice president, Commercial Sector, AMD. "Increasing performance levels at the expense of increasing power consumption is unacceptable in current and future processors. We look forward to working through the Power Forward Initiative to create and deploy new design automation approaches that reduce power effects of increased semiconductor device performance."
Getting Started with Common Power Format
Recognizing the need for a broad-based method of specifying power-management design intent across the entire design chain and for ensuring smooth collaboration and high-yield manufacturability, the Initiative members will have access to the first version of the Common Power Format (CPF). This new specification language addresses the limitation in the design automation tool flow by capturing the designer's intent for power management. The Common Power Format enables all design- and technology-related power constraints to be captured in a single file and applies that file across the design flow, providing a consistent reference point for design development and production.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
For more information, please contact: Michael Fournell Cadence Design Systems, Inc. 408-428-5135 Email Contact