Put on your walking shoes and take a tour across the show floor for an impromptu and decidedly un-scientific poll about what's going to be hot, or not, in San Francisco in July at the 43rd annual Design Automation Conference. There are 60+ responses included in this poll, and you'll know pretty quickly which were collected 'live' and which came in response to an e-mail requesting feedback.
Chuckle, if you will, at some of the market-speak here, but laugh at your own risk. Market-speak or not, there's going to be stuff going on at DAC. I think you should be there, and you probably agree. But, just in case you don't, there's even a nay-sayer - albeit Anon - in here for your reading pleasure.
And by the way, for those of you who would like to have put in your two bits - or 100 words - and didn't get the chance, we'll do this again in early July when DAC's more of a reality than it is at this time.
Warning: A number of people have told me that a) there is no buzz, or b) it's too soon because July's too far away. If that's how you feel, that's fine too.
Thanks a lot,
[Editor's Note: There were two versions of this e-mail. This one combines text from both.]
Anon - I have to ask the question: How long before the big EDA companies pull out of DAC completely? They state that it does not provide an effective return on investment and instead are putting their money into private traveling shows. Is this the whole story, or is it a continued part of their attempt to control the customer more? They have always hated allowing a prospective or actual customer leaving their booth or suite and to go and ask a competitor what they are doing to address what they just heard from another company. They want to control the customer and DAC does not allow them to set the rules.
Accellera - Accellera will hold an open membership meeting, hosting a Breakfast Panel with SystemVerilog users, and a SystemVerilog tutorial at DAC. Also, several Accellera Technical Committees will also hold informational meetings, and Birds-of-a-Feather sessions are planned. Accellera focuses on identifying new standards, development of standards and formats, and fostering the adoption of new methodologies required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. [Editor's Note: I'm going to be moderating the Accellera Breakfast Panel at 7:30 AM on July 26th. If you can drag yourself out of bed the morning after the Denali Party, I hope you'll join us.]
Adam Traidman, President at Chip Estimate (formerly Giga Scale IC) - We will make a major announcement in the run-up to DAC about progress towards our mission of aggregating IP, manufacturing, and economic data from across the supply chain to improve how designers estimate the size and cost of their chips. We believe that InCyte will become an even more significant tool this year. With 5,000 users and 30,000 chip estimations accomplished since our launch a year ago, we will move to the next level to support our goal of increasing designer productivity during the planning phase.
Alan Swahn, Vice President of Marketing & Business Development at Carbon Design Systems - At the Design Automation Conference, ESL will again be one of the hottest areas. Carbon Design Systems, a leader in virtual system prototyping solutions, will have a theater in their booth featuring presentations on advances in ESL design methodology. Topics will include system level modeling, architectural profiling, transaction-level modeling, RTL import into an ESL environment, and hardware-software co-debug.
Ashu Mausker, Vice President at Azuro - Azuro, a provider of innovative EDA tools that significantly reduce the power consumption of digital semiconductor chips, will be highlighting the latest version of our flagship product, PowerCentric at DAC 2006. PowerCentric is a revolutionary new low-power clock implementation solution that significantly reduces the dynamic power consumption of digital chips. PowerCentric brings together unique patent-pending approaches to clock-tree synthesis, clock-gate logic synthesis, and accurate average-case vectorless dynamic power analysis, to deliver a single unified clock design closure solution for power sensitive chip design teams.
Atul Sharan, President & CEO at Clear Shape Technologies - The DFM buzz will be deafening. The big EDA vendors have jumped on the bandwagon feet-first, marketing-first, products-maybe-or-maybe-not-much-later, noisily adding their DFM claims to the mix of approximately 40 'non-DFM' DFM start-ups. Attendees will have to troll through offerings to separate repackaged OPC and DRC products from true DFM tools that enable them to manage systematic manufacturing variations during design - BOTH geometry and parametric. Advice to DAC attendees? Ignore "random" noise and "systematically" look to vendors like Clear Shape that ALL major foundries have qualified, releasing hitherto untouchable FAB data/models, and being used by real designers. Ignore post-GDSII OPC offerings cleverly disguised as design tools.
Behrooz Zahiri, Senior Director of Product Marketing at Magma Design Automation - This year's DAC will prove that 65-nanometer designs are here and design teams are moving to it, to take advantage of lower die sizes and higher levels of integration. In doing so, though, they are struggling with the costly amount of manual work required to handle large designs, issues related to power consumption and DFM. Automation and the ability to address power and DFM throughout the flow is what's required to achieve profitability on 65-nanometer designs. DAC attendees can expect several technical sessions addressing these topics and companies such as Magma will exhibit products that solve such design challenges.
Brian Bailey, Chief Technologist at Poseidon Design Systems - One could claim that ESL tools have failed to address a compelling need. This could either be a problem with the tools, or that the need was not great enough. Multi-processor has started to become a significant platform for the server and desktop markets, and as this migrates into the embedded world, it will require a whole new class of tool. Those tools cannot just focus on the hardware; they have to address the software and systems aspects as well. Companies such as Poseidon Design Systems have recognized this trend and have the tools ready. Has the need grown sufficiently?
Charles Ng, Vice President of Worldwide Sales & Marketing at Kilopass Technology - Kilopass is an emerging supplier of embeddable, non-volatile memory IP implemented in a standard-logic CMOS process. The company has just announced that one of their customers, Zoran, has started to ship in volume their consumer IC products that contain Kilopass' memory IP. Kilopass will feature a number of their customer successes at DAC this year, showing how their non-volatile memory IP brings value to digital consumer ICs, mixed-signal ICs, secure ID storage, embedded boot-code, and firmware storage.