Yamaha Licenses Virage Logic Semiconductor IP for Next-Generation Mobile Phone Platform; Virage Logic's Reliability and Excellent Technical Support Are Key Factors in Yamaha's Selection Process

FREMONT, Calif.—(BUSINESS WIRE)—May 3, 2006— Extending a long-term standard cell technology licensing agreement, Virage Logic (Nasdaq: VIRL) today announced that Yamaha Corporation (Head Office: Hamamatsu, Shizuoka Prefecture, Japan; President: Shuji Ito) has strengthened its relationship by licensing components of Virage Logic's IPrima(TM) platform including embedded memories and standard cells.

Yamaha, a global leader in several businesses including musical instruments and consumer audio, will employ Virage Logic's Area, Speed and Power (ASAP) Memory(TM), High-Density (HD) and Ultra-Low-Power (ULP) memories and ASAP Logic(TM) Ultra-High-Density (UHD) standard cell libraries for its next-generation sound chip for multimedia phones (AudioEngine(TM)). Utilizing a combination of several low-power and very efficient density techniques, Virage Logic's silicon-proven intellectual property (IP) will provide Yamaha with significant power savings, a necessity for next-generation, battery-operated mobile phone applications.

"After an extended evaluation of commercially available semiconductor IP, we chose Virage Logic specifically because of their IP's quality, reliability and the fact that their components are silicon-proven in over hundreds of high-volume consumer designs," said Yukichi Ono, group leader at Yamaha's Semiconductor Division's LSI Development Department. "The results of the ASAP Ultra-Low-Power memory evaluation provided us with outstanding power savings. In addition, our IP selection criteria included access to superior technical support which Virage Logic has consistently provided us with."

"We are very pleased to see Yamaha extend its ASAP Logic technology licensing agreement to incorporate several of our ASAP High-Density and Ultra-Low-Power memories," said Jim Ensell, vice president of marketing and business development at Virage Logic. "We are confident that the IPrima platform components that Yamaha has selected will provide them with the significant power and area savings they need to extend their leadership with their next-generation Mobile Platform product line."

About IPrima Platforms

Virage Logic's IPrima platforms deliver integrated and technologically optimized semiconductor IP targeted for specific technology nodes, foundry processes and target applications. Each IPrima platform comprises some combination of Area, Speed and Power (ASAP) memories and/or Self-Test and Repair (STAR) memories, and ASAP Logic standard cell libraries and/or Base I/O Libraries.

The ASAP and STAR Memory product families offer the broadest portfolio of silicon-proven High-Density (HD), High-Speed (HS) and Ultra-Low-Power (ULP) memories spanning from 180nm to 65nm, and include single and dual-port ASAP SRAMs, single and dual-port STAR (Self-Test and Repair) SRAMs, single and dual-port RF (Register Files) and Read Only Memories (ROMs). The Ultra-Low-Power (ULP) memories are architected to provide low active power and low standby power. Virage Logic uses industry leading techniques such as multi-banking, clock management, periphery shutdown and array biasing to achieve up to a 15 times reduction in standby power and up to a five times reduction in active power.

The ASAP Logic Ultra-High-Density (UHD) standard cell library typically provides up to 30 percent smaller area when compared to conventional standard cell libraries. In addition, the UHD IP consumes 20 percent less dynamic power and up to seven times less static power.

About Virage Logic Corporation

Founded in 1996, Virage Logic Corporation (Nasdaq: VIRL) rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Now, as the company celebrates its 10th anniversary, it is a global leader in semiconductor IP platforms comprising embedded memories, logic, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company uses its FirstPass-Silicon(TM) Characterization Lab for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.

Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995:

Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to industry and company trends, business outlook and products. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to improve its operations; its ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2005, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website ( www.viragelogic.com) or from the SEC's website ( www.sec.gov), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.

All trademarks and copyrights are property of their respective owners and are protected therein.

Virage Logic Corporation
Sabina Burns, 510-743-8115

Email Contact
McClenahan Bruer Communications
Kerry McClenahan, 503-546-1002

Email Contact

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy