SEQUANS Standardizes on Synopsys VCS, System Studio and Formality Solutions for Verification of Broadband Wireless Access Chips

Synopsys Discovery(TM) Verification Platform Provides a Complete Verification Solution From System Level Through RTL to Gates

MOUNTAIN VIEW, Calif., March 28 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that SEQUANS Communications, a fabless semiconductor company that develops end-to-end standards-based silicon for broadband wireless access, has adopted key components of the Synopsys Discovery(TM) Verification Platform to establish a leading-edge chip verification process. Sequans has standardized on the Synopsys VCS(R) comprehensive RTL verification solution, System Studio for algorithm design and system-level verification and the Formality(R) formal equivalence checker to ensure consistency between RTL and chip implementations. Sequans has successfully released Base Station and Subscriber Station chips, compliant with the IEEE 802.16-2004 standard. Both chips were developed in record time, and Synopsys' tools helped minimize risks and delays. Sequans plans to soon release its chips for the mobile WiMAX/WiBro market and is using Synopsys tools to help ensure the best time-to-market schedule.

"We selected Synopsys for our verification needs because they provide a complete solution from algorithm design to implementation," said Bertrand Debray, Sequans vice-president of Engineering. "It is important to us that an electronic system-level (ESL) tool for algorithm design and analysis be linked closely with the RTL verification process. Synopsys provides this connection with its well-integrated combination of System Studio and the VCS solutions. In addition, the Formality formal equivalency checking process ensures that our RTL is consistent with our final ASIC implementations."

"Synopsys' Discovery Verification Platform is the industry's leading system, RTL and gate-level verification solution. The VCS solution's integrated high-performance testbench-based verification environment is ideal for verifying complex chips in the rapidly growing WiMAX space," said George Zafiropoulos, vice president of Marketing, Verification Group, Synopsys, Inc. "This integration, when combined with our Reference Verification Methodology (RVM), yields a complete, high-performance process for verifying the industry's largest and most complex chips."

Synopsys Discovery Verification Platform

The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, DesignWare(R) verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemC(TM) and OpenVera(R), and Synopsys' proven Reference Verification Methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at .

NOTE: DesignWare, Formality, OpenVera, Vera and VCS are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Editorial Contacts:
     Isela Warner
     Synopsys, Inc.
Email Contact

     Khyati Shah
Email Contact

CONTACT: Isela Warner of Synopsys, Inc., +1-650-584-1644, or
Email Contact; or Khyati Shah of Edelman, +1-650-429-2769, or
Email Contact, for Synopsys, Inc.

Web site:

Review Article Be the first to review this article
CST: Webinar November 9, 2017


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise