"Given his insightful contributions as a member of Jasper's TAB, and his skillful establishment and management of our development site in Brazil, Claudionor is ideally suited to lead our growing multi-national engineering team," said Kathryn Kranen, president and CEO of Jasper. "His depth of knowledge and experience in formal verification, combined with his excellent management skills and visionary leadership, will serve to drive Jasper's industry-leading formal technology forward and help to deliver exceptional value to our customers."
"Having been involved with Jasper since the founding of its technical advisory board, I am extremely impressed with the engineering team and look forward to serving in a leading role with this company," said Claudionor Coelho. "Jasper's name is synonymous with systematic verification, and I look forward to leading this talented multi-national team as we advance the state of formal verification and continue to make it a competitive advantage for our customers."
Before joining Jasper Design Automation, Claudionor Coelho served in technical and upper management positions in several US companies, including Integrated Information Technology (Nasdaq:EGHT), where he led the formal verification of a pipelined high-performance processor, and in Verplex Systems, now part of Cadence (Nasdaq:CDNS), where he directed the BlackTie team and was responsible for the development of OVL. He was also a founder of several successful startups, and he was a counselor for FirCapital Partners in startup strategy and technology. Coelho obtained his BSEE, summa cum laude, and MSCS from the Federal University of Minas Gerais in Belo Horizonte, Brazil; his PhD in EE/CS from Stanford University; and his MBA from IBMEC/MG. Dr. Coelho has written award-winning papers and books, and was a contributing author to "Advanced Formal Verification" from Kluwer Academic Publishers. He is also an Associate Professor at the Computer Science Department at the Federal University of Minas Gerais, Brazil.
About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company's flagship product, JasperGold(R) Verification System, is the first verification product to deliver systematic complete verification, and accomplishes this task within predictable, finite schedule constraints. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules. For further details on how to achieve complete verification, and improve verification productivity, predictability and verification reuse, please visit http://www.jasper-da.com.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold and Formal Testplanner are trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.
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