Cadence Unveils Advanced Manufacturing-Aware Chip-Optimization Technology; Three-Dimensional Space-Based Optimization Approach Addresses Customers' Most Pressing DFM and DFY Challenges

SAN JOSE, Calif.—(BUSINESS WIRE)—Jan. 30, 2006— Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its new groundbreaking manufacturing-aware chip optimization product Cadence(R) Chip Optimizer, an innovative, silicon-proven full-chip optimization system. Cadence Chip Optimizer is used after conventional place and route and before design tape out to improve the yield, manufacturability and performance of complex IC designs.

Cadence developed Chip Optimizer as part of its growing family of world-class manufacturing and yield-aware offerings aimed at addressing the industry's most pressing design for manufacturing (DFM) and design for yield (DFY) challenges. Conventional IC implementation tools create an oversimplified model of interconnect and foundry manufacturing process rules. Cadence Chip Optimizer uses a three-dimensional space-based optimization approach which models, analyzes and optimizes true shapes and intervening physical spaces. This provides a more accurate and realistic 'map' of the design, and clearly indicates where important optimizations may be made. Shapes and spaces can be positioned in the exact configuration and location required to correct for sub wavelength, spacing and topological effects. This approach enables greater precision and flexibility in optimization.

"Cadence and ATI have worked together for more than 3 years to bring a critical set of manufacturing optimizations into the design phase," said Greg Buchner, vice president of engineering at ATI. "We have used the Cadence Chip Optimizer technology on more than 10 tapeouts at multiple foundries, including the graphics processor for the Microsoft Xbox 360 and the world's fastest consumer PC graphics processor, our recently announced Radeon X1900 XTX. Cadence Chip Optimizer plays a vital and ever-growing role in helping ATI achieve our design, manufacturability and yield goals."

This technology performs interconnect topology optimizations, while taking into consideration manufacturing and electrical constraints on digital or custom designs.

"Cadence Chip Optimizer has performed flawlessly on our 65-nanometer microprocessor design methodology," said Mark Papermaster, vice president of Microprocessor and Systems Technology Development at IBM Corp. "The truly collaborative partnership we have with the Cadence Chip Optimizer team for the last 3 1/2 years has been an ideal working relationship. The extensive time we spent together understanding and addressing the design for yield and manufacturing challenges was key. We achieved closure to our design goals on schedule, in an automated and predictable manner."

Cadence Chip Optimizer is built on innovative technology developed in Cadence's Project Catena technology incubator and can be applied to a broad range of design styles and process nodes. This is demonstrated by tapeouts and production silicon for high-volume designs at leading-edge process nodes for markets including high-end consumer, graphics processors and microprocessors.

"Unlike many contemporary technology developments purporting to solve manufacturability issues at advanced process nodes, this product represents a fundamental breakthrough in chip scale physical and electrical modeling," said Ted Vucurevich, CTO of Advanced Research and Development at Cadence. "Integrated with incremental sign-off quality analysis and advanced optimization capability, this technology allows us to accurately handle today's most demanding sub-wavelength lithography and manufacturing process rules, and sets the stage to efficiently evolve our capabilities in accordance with the currently published International Semiconductor Association roadmap."

Cadence Chip Optimizer works seamlessly with the Cadence Encounter(R) digital IC design platform and the Virtuoso(R) custom design platform. It is a native application on the OpenAccess database.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Virtuoso, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.



Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302

Email Contact

Rating:


Review Article Be the first to review this article

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise