It is clear that changes in the way end users listen to music, watch TV and movies, and communicate via cell phones has already had a significant impact on the consumer electronics industry and therefore on semiconductor companies and their EDA suppliers. The semiconductor companies have shifted their focus from telecommunications toward consumer electronics. This shift requires a change in the tools that EDA vendors develop. For example the need for lower power chips to support longer battery life for mobile devices has spurred many EDA startups offering power management tools, power grid design tools, and power simulation software as described in recent editorials. The question is whether some of the other trends mentioned earlier in this editorial will also have an impact on the EDA industry.
We know that
1. the younger generation has flaunted copyright laws on a massive scale
2. the younger generation has experienced free legal software like Google which undercuts their perceived value of software
3. growth in EDA is coming from countries with little history in the area of intellectual property protection
4. growth in EDA is coming from countries where all costs (labor, facilities, transportation) are substantially lower than the US and Europe
5. global development operations follow the sun enabling a single piece of code to be used around the clock
6. Internet speed will increase while security hopefully will improve
7. pricing for high end mechanical CAD products have plunged over time forcing major players to expand their product portfolios into product data management and collaboration along with associated services.
On the other hand it would be naïve to think that the changes that have happened in other industries will not have some parallels in the EDA industry possibly in the way software is price, packaged or delivered.
The top articles over the last two weeks as determined by the number of readers were
Leakage Power Optimization With Dual-Vth Library In High-Level Synthesis - Technical Paper from DAC 2005 The paper presents a heuristic algorithm for leakage power optimization based on the maximum weight independent set problem. A dual threshold voltage (Vth) technique is used to reduce leakage energy consumption in a data flow graph.
Texas Instruments Introduces New Web Design Tailored for Electronic Design Engineers The new Web design makes it easier and quicker for design engineers to access product information and support materials critical for their high-performance designs.
Your ASIC design better work on silicon the first time! Designs which are not functionally verified beyond a string of doubt, ensuring that the design implementation conforms exactly to the architecture specifications and will work under all possible scenarios of usage at all times, never see their day on silicon. An adequately verified ASIC design entails a mandatory spending of at least 50% of the total design effort on design verification.
Chipworks first inside Microsoft's Xbox 360 silicon Chipworks monitors advanced semiconductors and systems, and creates detailed reports of what is inside technology. Their customers use this information to maintain their competitive advantage, benchmark their innovations and improve their business costs.
Structured ASIC to Solve Cost and Design Issues in the IC Industry The structured ASIC cut the nonrecurring engineering (NRE) expenses by more than 85.0 per cent in derivative chips and is set to become a crucial element in the upcoming deep sub-micron (DSM) designs.
Synopsys Posts Financial Results for Fourth Quarter and Full-Year Fiscal 2005 For the fourth quarter of fiscal 2005, Synopsys reported revenue of $254.8 million, an 11 percent increase compared to $230.6 million for the fourth quarter of fiscal 2004. Revenue for fiscal year 2005 was $991.9 million, a decrease of 9 percent from the $1.09 billion in fiscal 2004. Lower revenue in fiscal 2005 reflects the company's shift to an almost fully ratable license model initiated in the fourth quarter of fiscal 2004. See upcoming EDA industry quarterly report.
Other EDA News
Memory Access Optimization Through Combined Code Scheduling, Memory Allocation, and Array Binding in Embedded System Design - Technical Paper from DAC 2005
Submissions Now Accepted for DAC- ISSCC-Sponsored Student Design Contest
Logic Soft Errors in Sub-65nm Technologies - Design and CAD Challenges - Technical Paper from DAC 2005
FyreStorm Uses Sequence's Low Power Tools for its Mobile Power Management Solution; FyreStorm Slashes Power Significantly with PowerTheater; Uses CoolTime for Power Grid Sign-Off
Silicon Canvas Offers a Complete Analog Design Platform with the Release of Laker ADP
austriamicrosystems Releases New Version of Design Kit for the Latest Release of Mentor Graphics' IC Design Flow
VaST Systems Technology and Gaia System Solutions Announce Initiative in Japan for Development of Automotive Electronics Using VaST Virtual System Prototyping Solutions
ESL: Tales from the Trenches - Technical Paper from DAC 2005
Virage Logic Senior Executives Tapped to Deliver Industry Keynotes
Cadence Seeks Silicon Valley Beneficiary for 2006 Stars & Strikes Fundraiser
Cradle Rocks With Sequence's PowerTheater; "PowerTheater Reduces Power Consumption by 30 Percent and Demonstrates Accuracy Within 10 Percent of Silicon"
A Noise-Driven Effective Capacitance Method With Fast Embedded Noise Rule Calculation for Functional Noise Analysis - Technical Paper from DAC 2005 Agere Systems Accelerates Tapeout of High-Performance SOC with Synopsys IC Compiler
Altium Releases Altium Designer 6.0
PCB Enhancements Head Altium Designer 6.0 Release
Other IP & SoC News
Hiroshima Elpida Commences Mass Production of 90 nm DRAM Chips on New 300 mm Wafer Production Line; Newly Expanded E300 Fab Targets 54,000 Wafers per Month, the Largest Semiconductor Capacity in Japan
Renesas Technology and Grandis to Collaborate on Development of 65 nm MRAM Employing Spin Torque Transfer
Tundra Semiconductor releases Q2-fiscal 2006 financial results
Len Perham to Discuss 'The Future of Technology in the Silicon Valley and Beyond' in Executive Panel
Globetech Solutions adds CE-ATA to portfolio of Verification IP
SafeNet Announces High End Integrated Security Processor for SME Networking Equipment; SafeXcel-5160 is the Most Cost Effective Security Processor for Gigabit Class SME Appliances
Competition Rises in the Advanced Television Semiconductor Market as Future Predictions Estimate the Market to Grow to $1.9 billion in 2009
Signum Systems Introduces Low Cost, Full-Featured JTAG Emulator for TI C2000(TM) Digital Signal Controllers